The level-1 calorimeter trigger consists of a preprocessor (PP), a cluster processor (CP), and a jet/energy-sum processor (JEP). The CP and JEP receive digitised trigger-tower data from the preprocessor and produce regions-of-interest (RoIs) and trigger multiplicities. The latter are sent in real time to the central trigger processor (CTP) where the level-1 decision is made. On receipt of a level-1 accept, readout driver modules (RODs) provide intermediate results to the data acquisition (DAQ) system for monitoring and diagnostic purposes. RoI information is sent to the RoI builder (RoIB) to help reduce the amount of data required for the level-2 trigger. The level-1 calorimeter trigger system at the test beam consisted of 1 preprocessor module, 1 cluster processor module, 1 jet/energy module and 2 common merger modules. Calorimeter energies were successfully handled throughout the chain and trigger objects sent to the CTP. Level-1 accepts were successfully produced and used to drive the readout path. Online diagnostics were made using 4 RODs. Energy histograms were plotted and the integrity of data between the different modules was checked. All ATLAS detectors in the test beam were able to build full events based on triggers delivered by the calorimeter trigger system.

The architecture of the ATLAS Level-1 Calorimeter Trigger system (L1Calo) is presented. Common approaches have been adopted for data distribution, result merging, readout, and slow control across the three different subsystems. A significant amount of common hardware is utilized, yielding substantial savings in cost, spares, and development effort. A custom, high-density backplane has been developed with data paths suitable for both the em//spl tau/ cluster processor (CP) and jet/energy-summation processor (JEP) subsystems. Common modules also provide interfaces to VME, CANbus and the LHC timing, trigger and control system (TTC). A common data merger module (CMM) uses field-programmable gate arrays (FPGAs) with multiple configurations for summing electron/photon and /spl tau//hadron cluster multiplicities, jet multiplicities, or total and missing transverse energy. The CMM performs both crate- and system-level merging. A common, FPGA-based readout driver (ROD) is used by all of the subsystems to send input, intermediate and output data to the data acquisition (DAQ) system, and region-of-interest (RoI) data to the level-2 triggers. Extensive use of FPGAs throughout the system makes the trigger flexible and upgradable, and several architectural choices have been made to reduce the number of intercrate links and make the hardware more robust.

The ATLAS Level-1 Calorimeter Trigger consists of a Preprocessor, a Cluster Processor (CP), and a Jet/Energy-sum Processor (JEP). The CP and JEP receive digitized trigger-tower data from the Preprocessor and produce trigger multiplicities and total and missing energy for the final trigger decision. The trigger also provides region-of-interest information for the Level-2 trigger and intermediate results of the data acquisition system for monitoring and diagnostics by using Readout Driver modules. The JEP identifies and localizes jets, and sums total and missing transverse energy information from the trigger data. The Jet/Energy Module (JEM) is the main module of the JEP. The JEM prototype is designed to be functionally identical to the final production module for ATLAS and to have the full number of channels. Three JEM prototypes have been built and successfully tested. Various test vector patterns were used to test the energy summation and the jet algorithms. Data communication between adjacent JEMs and all other relevant modules of the JEP has been tested. Recent test results using the JEM prototypes are discussed.

At the full LHC design luminosity of 1034cm−2s−1, there will be approximately 109 proton–proton interactions per second. The ATLAS level-1 trigger is required to have an acceptance factor of ∼10−3. The calorimeter trigger covers the region |η|⩽5.0, and φ=0 to 2π. The distribution of transverse energy over the trigger phase space is analysed to identify candidates for electrons/photons, isolated hadrons, QCD jets and non-interacting particles. The Cluster Processor of the level-1 calorimeter trigger is designed to identify transverse energy clusters associated with the first two of these. The algorithms based on the trigger tower energies which have been designed to identify such clusters, are described here. The algorithms are evaluated using an FPGA. The reasons for the choice of the actual FPGA being used are given. The performance of the FPGA has been fully simulated, and the expected latency has been shown to be within the limits of the time allocated to the cluster trigger. These results, together with the results of measurements made with real data into a fully configured FPGA, are presented and discussed.

The final Pre-Precessor Multi-Chip Module (PPrMCM) of the ATLAS Level-1 Calorimeter Trigger is presented. It consists of a four-layer substrate with plasma-etched vias carrying nine dies from different manufacturers. The task of the system is to receive and digitize analog input signals from individual trigger towers, to perform complex digital signal processing in terms of time and amplitude and to produce two independent output data streams. A real-time stream feeds the subsequent trigger processors for recognizing trigger objects, and the other provides deadtime-free readout of the Pre-Processor information for the events accepted by the entire ATLAS trigger system. The PPrMCM development has recently been finalized after including substantial experience gained with a demonstrator MCM.

The level-1 calorimeter trigger consists of three subsystems, namely the Preprocessor, electron/photon and tau/hadron Cluster Processor (CP), and Jet/Energy-sum Processor (JEP). The CP and JEP will receive digitised calorimeter trigger-tower data from the Preprocessor and will provide trigger multiplicity information to the Central Trigger Processor and region-of-interest (RoI) information for the level-2 trigger. It will also provide intermediate results to the data acquisition (DAQ) system for monitoring and diagnostic purposes. This paper will outline a readout system based on FPGA technology, providing a common solution for both DAQ readout and RoI readout for the CP and the JEP. Results of building a prototype readout driver (ROD) module will be presented, together with results of tests on its integration with level-2 and DAQ modules.

The architecture of the ATLAS Level-1 Calorimeter Trigger has been improved and simplified by using a common module to perform different functions that originally required three separate modules. The key is the use of FPGAs with multiple configurations, and the adoption by different subsystems of a common high-density custom crate backplane that takes care to make data paths equal widths and includes minimal VMEbus. One module design can now be configured to count electron/photon and tau/hadron clusters, or count jets, or form missing and total transverse-energy sums and compare them to thresholds. In addition, operations are carried out at both crate and system levels by the same module design.

This paper presents an evaluation of the proposed LVDS serial data transmission scheme for the ATLAS level-1 calorimeter trigger. Approximately 7000 high-bandwidth links are required to carry data into the level-1 algorithmic processors from the Preprocessor crates. National Semiconductor’s Bus LVDS serialiser/deserialiser chipsets offer low power consumption at low cost and synchronous data transmission with minimal latency. Test systems have been built to measure real-time bit-error rates using pseudo-random binary sequences. Results show that acceptable error rates better than 10 13 per link can be achieved through compact cable connector assemblies over distances up to 20 m.

The ATLAS level-1 calorimeter trigger will utilise a number of advanced technologies, many of which have already been successfully demonstrated. To evaluate the different technologies associated with the important areas of high-speed data transport a large demonstrator system has been designed and operated during the last two years, using signals from prototype calorimeters in the ATLAS test-beam.Using this system, inter-crate data transmission and reception have been demonstrated at over 1.4 Gbyte/s, with individual links running at up to 1.6 Gbaud, Operating with 160 Mbit/s signals across a transmission-line backplane, custom transceiver ASICs have achieved inter-module data fanout at peak rates above 800 Mbyte/s. With the addition of Further modules, the system was extended to emulate a vertical slice through the ATLAS level-1 calorimeter trigger.We present here the results from these tests, including measurements of bit-error rates across different data paths.

The proposed level-1 calorimeter trigger system for ATLAS relies upon several key technologies which we have been testing in a demonstrator programme. We describe here the final phase of this programme, which concentrates on crucial aspects of high-speed data transmission inherent in the trigger architecture while operating with signals from prototype ATLAS calorimeters. The 36-channel trigger demonstrator system has been designed to provide a flexible infrastructure for the study of alternative techniques of communication between the calorimeters and the trigger processor, including both analogue links and high-speed digital optical and electrical links operating at up to 1.6 Gbaud. Data fan-out at 160 Mbit/s between trigger processor modules using serialising Application Specific Integrated Circuits (ASICs) driving transmission-line backplanes is also evaluated. A programmable timing system re-synchronises all channels before pipeline processing by ASICs executing an electromagnetic cluster-finding algorithm. Some preliminary results are presented from the operation of this demonstrator system installed in the ATLAS test-beam at CERN

Beam tests of a first-prototype electromagnetic calorimeter trigger processor for LHC experiments are described. The synchronous, pipelined, digital processor built with ASICs, was successfully operated at the full LHC bunch-crossing frequency of 40 MHz. Real data signals were obtained from a liquid argon electromagnetic calorimeter. The measured performance of the electron/photon trigger algorithm is compared with Monte Carlo simulations.

This report describes the 1991 implementation of the data acquisition system of the OPAL detector at LEP including the additional services and infrastructure necessary for its correct and reliable operation. The various tasks in this “on-line” environment are distributed amongst many VME subsystems, workstations and minicomputers which communicate over general purpose local area networks and special purpose buses. The tasks include data acquisition, control, monitoring, calibration and event reconstruction. The modularity of both hardware and software facilitates the upgrading of the system to meet new requirements.

A prototype first-level calorimeter trigger for use at LHC is described. The trigger is designed to operate on analogue signals sampled every 15 ns, the original design period for LHC. The prototype system takes in signals from a 6x6 array of calorimeter cells. These are digitised by FADCs and are then sent to a cluster finding module which contains nine ASICs based on a 0.8 micron CMOS gate array. Each ASIC searches for isolated energy clusters within the array and also calculates the sum of the energy in all 16 cells. The energy threshold of the cluster and of the isolation window are field programmable. The performance of the trigger has been evaluated both with test systems and in real conditions connected to a liquid-argon electromagnetic calorimeter in a test beam at CERN. The latency of this pipelined trigger system is 175 ns, including digitisation and digital processing.