Neuromorphic computing based on artificial synapses requires devices capable of gradual, repeatable, and energy-efficient conductance modulation. Ionically gated transistors are promising candidates because their ion dynamics naturally produce synaptic behavior under low-voltage operation. However, how key device characteristics-conductance range, number of accessible conductance states N, and weight-update nonlinearity β-jointly influence neural network performance remains insufficiently understood. Here, we investigate MoS2-based ionically gated synaptic transistors using a combined experimental and modeling framework that links device physics to hardware-aware artificial neural network (ANN) simulations across image-classification tasks of varying complexity. We show that under fixed-amplitude pulsing, increasing N introduces a fundamental trade-off: finer weight resolution is accompanied by stronger update nonlinearity. ANN simulations further reveal that, within the nonlinearity range studied here, classification accuracy is governed by a task-dependent optimal weight resolution rather than a simply maximized number of states. To overcome the nonlinear weight updates, we employ a physics-informed transient model to develop a predictive pulse-engineering algorithm and experimentally demonstrate that it can linearize synaptic weight evolution in the same device. These linearized updates improve ANN accuracy by 1.5%-5.2% for MNIST, 4.0%-5.2% for FMNIST, and 1.2%-12% for KMNIST across the tested state numbers, establishing a quantitative link between device-level dynamics and neural network performance in ionically gated synaptic transistors.

Deep neural networks (DNNs) deployed on resource-constrained neuromorphic hardware face three concurrent challenges: the need for model compression through pruning, vulnerability to adversarial input perturbations, and susceptibility to hardware-induced weight faults such as stuck-at-zero errors. While each of these factors has been studied in isolation, their combined effects on model reliability have received little attention. This paper presents an empirical investigation of how pruning, adversarial training, and hardware fault injection interact to affect the robustness of convolutional neural networks. Using a compact three-layer CNN trained on MNIST, we conduct three experiments: (1) comparing the fault tolerance of naturally and adversarially trained models under simultaneous hardware faults and adversarial attacks, (2) evaluating how pruning affects adversarial robustness, and (3) characterizing the joint accuracy surface across fault rates, adversarial perturbation magnitudes, and pruning levels. Our results show that adversarial training improves robustness against input perturbations but increases sensitivity to stuck-at-zero weight faults. Contrary to intuition, pruning did not significantly increase fault sensitivity, and varying the pruning level had little effect across fault rates and attack strengths. These results highlight the need to jointly consider adversarial robustness and hardware reliability.

Short-term plasticity (STP) is fundamental to temporal information processing in biological neural systems but remains difficult to realize efficiently in neuromorphic hardware. Memristive electrochemical random-access memory (ECRAM) devices naturally exhibit non-equilibrium ionic dynamics that produce transient conductance modulation; however, these behaviors are typically treated as undesirable variability or tolerated as side effects in memory-centric computing paradigms. In this work, we instead transform these volatile dynamics from a tolerated device artifact into a computational resource through a cross-layer device-circuit-system co-design framework. We introduce a delay-feedback leaky integrate-and-fire (LIF) neuron architecture co-designed with ECRAM synapses that exploits activity-dependent conductance modulation with negligible additional circuit overhead. The architecture integrates ECRAM-based synapses with a tunable delay-feedback spike-generation path, enabling transient device dynamics to directly modulate neuron excitability and synaptic efficacy. We used experimentally characterized ECRAM devices exhibiting transient conductance modulation (1.5 KOhms per spike) to develop a compact behavioral model suitable for circuit-level simulation. Circuit simulations demonstrate two key STP behaviors – synaptic facilitation and intrinsic excitability modulation – while consuming 2 pJ per spike, and the same device-driven mechanisms extend across multiple neuron topologies. Network-level analysis further demonstrates frequency-selective spike processing, allowing individual synapses to act as tunable temporal filters within spiking neural networks. This work demonstrates that non-equilibrium ECRAM dynamics can serve as a native hardware substrate for STP and temporal computation in neuromorphic circuits.

This brief investigates the limitations on throughput and delay chain length in time-domain neuromorphic computing and proposes solutions to overcome these challenges. Through the employment of clock optimization, cascaded delay cells, and pulse-width expander cells, this brief demonstrates significant throughput and scalability improvements over the current state of the art. Analyses reveal critical relationships between chain length, variability, and supply voltage, highlighting that increasing chain length improves variability and reduces sensitivity to supply scaling. Applied to a CNN, tested on the MNIST dataset, the proposed designs maintain robust accuracy with less than 1% degradation across a range of sigma/mu values, even under weight variation. The system achieves 0.57 fJ energy/op, with throughput as high as 2432 GOPS. The findings underscore the advantage of these delay cells for high-throughput, low variability, and energy-efficient time-domain neuromorphic systems.

This paper presents a compact analog dendritic cell that mimics key behaviors of biological dendrites for time-domain neuromorphic computing. The proposed architecture generates plateau potentials based on the amplitude and duration of incoming spatiotemporal spikes. It enables energy-efficient, scalable dendritic operations using a small number of transistors per synaptic input. Operating at 1V, it achieves an efficiency of 111.4 fJ per plateau potential generation. Performance was evaluated across various spiking activity levels and dendrite configurations. The circuit was also integrated into a spiking neural network using a modified BindsNET simulator to demonstrate its utility in detecting complex spatiotemporal patterns. Results confirm the viability of compact time-domain dendritic circuits for biologically inspired, efficient neuromorphic computing.

The training of neural networks is a compute-intensive task that, in current classical implementations, relies on gradient descent algorithms and a certain learning rate that controls the granularity of the search for a solution. This article explores a new hybrid quantum-classical approach, which is not only novel for exploding quantum computing to partially solve the problem, but also for being the first approach that adjusts the learning rate with exact information pertaining to the solution of this training problem. The quantum adaptive learning rate approach is tested in a proof-of-concept classification problem. Key aspects of the practical implementation of the Harrow-Hassidim-Lloyd quantum algorithm are discussed.

The large energy costs of advanced AI models precludes their direct deployment in resource-constrained edge applications. Neuromorphic computing addresses this problem through the design of energy-efficient hardware that accomplishes AI tasks through neuroscience-inspired computational principles. In this talk, we discuss our current efforts related to the design of neuromorphic systems that perform computations in the time domain. The time-domain paradigm employs cascaded configurable delay cells based on emerging memory devices to perform multiply-accumulate operations. Delay cell optimizations and tradeoffs between energy, latency, and variability will be discussed. Implementation of neural networks using the time-domain approach will presented along with the impacts of variations on classification performance. The talk will conclude with opportunities and challenges related to time-domain neuromorphic computing for next-generation resource-constrained AI systems.

This paper proposes a new adversarial attack strategy against neuromorphic systems using analysis of power consumption. Specifically, we show that neuromorphic designs based on non-volatile memory crossbars can leak important information about loss sensitivity in their power profile. Adversaries can use this information to craft evasion attacks even if they don’t know the dataset that the model was trained on. In our experiments, we show that these types of attacks are effective against both single-layer and multilayer neuromorphic implementations of neural networks, and they can be made query-efficient through Bayesian optimization. We also provide theoretical insights into the relationship between the loss sensitivity and the power consumption measurements, showing that, for single-layer networks, the correlation coefficient of these two metrics scales inversely with the square root of the input size. Finally, this paper proposes that low bitwidth quantization could be an effective defense strategy against the class of attacks discussed herein.

As artificial intelligence (AI) systems grow increasingly complex, efficiently processing billions of Multiply-Accumulate (MAC) operations while maintaining low power consumption and minimal latency becomes critical. Digital architectures offer high precision but demand significant area and energy, whereas analog approaches are more efficient but suffer from noise accumulation and scalability challenges. Time-domain (TD) computing emerges as a compelling alternative, leveraging signal transition timing to bridge the gap between digital precision and analog efficiency. This work explores TD neuromorphic computing using memristors and Electro-Chemical RAM (ECRAM) to enhance delay-based MAC operations. A key challenge—limited throughput due to accumulated delays—is analyzed and overcome through novel architectures. Results from a 55nm CMOS implementation demonstrate significant improvements in scalability and performance. Integrating ECRAM devices into our time-domain compute cells offers an even more effective pathway to enhancing performance, efficiency, and throughput in our architecture. Collectively, this paper underscores the potential of TD neuromorphic architectures for next-generation AI hardware.

This work evaluates the performance of ferroelectric field-effect transistors (FeFETs) and memristors as nonvolatile memory (NVM) elements for time-domain (TD) neuromorphic computing. Key metrics considered include energy per operation, throughput, mismatch sensitivity ($\sigma / \mu$), and cell area. We use our high-efficiency TD computing cell as the platform for this analysis. Simulations indicate that FeFET-based implementations achieve operating frequencies exceeding 30 MHz while occupying only 33% of the area of an equivalent memristor-based circuit, though with higher energy consumption. The three-terminal nature of the FeFET also offers performance advantages that two-terminal memristor-based implementations can only replicate through more complex cell architectures. These performance benefits, along with their compatibility with existing CMOS processes, position FeFETs as a strong candidate for neuromorphic TD computing applications.

Neuromorphic computing offers a low-power, parallel alternative to traditional von Neumann architectures by addressing the sequential data processing bottlenecks. Electric double layer-gated transistors (EDLTs) resemble biological synapses with their ionic response and offer low power operations, making them suitable for neuromorphic applications. A critical consideration for artificial neural networks (ANNs) is achieving linear and symmetric plasticity (i.e. weight updates) during training, as this directly affects accuracy and efficiency. This study uses finite element modeling to explore EDLTs as artificial synapses in ANNs and investigates the underlying mechanisms behind the nonlinear weight updates observed experimentally in previous studies. By solving modified Poisson-Nernst-Planck equations, we examined ion dynamics within an EDL capacitor and their effects on plasticity, revealing that the rates of EDL formation and dissipation are concentration-dependent. Fixed-magnitude pulse inputs result in decreased formation and increased dissipation rates, leading to nonlinear weight updates. For a pulse magnitude of 1 V, both 1 ms 500 Hz and 5 ms 100 Hz pulse inputs saturated at less than half of the steady state EDL concentration, limiting the number of accessible states and operating range of devices. To address this, we developed a predictive linear ionic weight update solver (LIWUS) in Python to predict voltage pulse inputs that achieve linear plasticity. We then evaluated an ANN with linear and nonlinear weight updates on the Modified National Institute of Standards and Technology classification task. The ANN with LIWUS-provided linear weight updates required 19% fewer (i.e. 5) epochs in both training and validation than the network with nonlinear weight updates to reach optimal performance. It achieved a 97.6% recognition accuracy, 1.5-4.2% higher than with nonlinear updates, and a low standard deviation of 0.02%. The network model is amenable to future spiking neural network applications, and the performance with linear weight updates is expected to improve for complex networks with multiple hidden layers.

Under the nearing error-corrected era of quantum computing, it is necessary to understand the suitability of certain post-NISQ algorithms for practical problems. One of the most promising, applicable and yet difficult to implement in practical terms is the Harrow, Hassidim and Lloyd (HHL) algorithm for linear systems of equations. An enormous number of problems can be expressed as linear systems of equations, from Machine Learning to fluid dynamics. However, in most cases, HHL will not be able to provide a practical, reasonable solution to these problems. This paper's goal inquires about whether problems can be labeled using Machine Learning classifiers as suitable or unsuitable for HHL implementation when some numerical information about the problem is known beforehand. This work demonstrates that training on significantly representative data distributions is critical to achieve good classifications of the problems based on the numerical properties of the matrix representing the system of equations. Accurate classification is possible through Multi-Layer Perceptrons, although with careful design of the training data distribution and classifier parameters.

Neuromorphic computing is a brain-inspired approach to hardware and algorithm design that efficiently realizes artificial neural networks. Neuromorphic designers apply the principles of biointelligence discovered by neuroscientists to design efficient computational systems, often for applications with size, weight and power constraints. With this research field at a critical juncture, it is crucial to chart the course for the development of future large-scale neuromorphic systems. We describe approaches for creating scalable neuromorphic architectures and identify key features. We discuss potential applications that can benefit from scaling and the main challenges that need to be addressed. Furthermore, we examine a comprehensive ecosystem necessary to sustain growth and the new opportunities that lie ahead when scaling neuromorphic systems. Our work distils ideas from several computing sub-fields, providing guidance to researchers and practitioners of neuromorphic computing who aim to push the frontier forward.

We present a low-power, low-area delay cell topology for time-domain (TD) neuromorphic computing. Each cell computes partial dot product operations using current summation and the result is accumulated by chaining delay cells together. An alternative clocking scheme for the delay chains is proposed that requires no additional area and can nearly 2x the throughput. In addition, the application of TD wave-pipelining is proposed to further improve throughput. These techniques were applied to a 64-input delay chain and to the design of a 3-input TD XOR gate. With the delay chain, up to a 11.54x speedup was observed. The proposed wave-pipelining provides larger speedups for longer delay chains, such as would be utilized by neural networks.

Artificial Neural Networks (ANNs) are powerful models that can learn underlying nonlinear structures within data, such as images, sounds, and sentences. However, researchers have found a significant unsolved problem with ANNs: small perturbations in input data or within the network’s parameters can cause the network to output incorrect predictions or classifications. This vulnerability becomes even more dangerous as models are loaded onto special-purpose chips and computing devices that may be vulnerable to attackers. To address this issue, we investigate the effects of activation function perturbations using foundational mathematical theory within neural networks. We compare our theoretical results with two feed-forward neural networks trained and evaluated on the MNIST dataset. Our findings suggest that even subtle perturbations in activation functions and parameters can have a significant impact on the performance of ANNs. Our methods are effective at both strengthening and destroying ANNs.

Spiking neural network (SNN) hardware has gained significant interest due to its ability to process complex data in size, weight, and power (SWaP) constrained environments. Memristors, in particular, offer the potential to enhance SNN algorithms by providing analog domain acceleration with exceptional energy and throughput efficiency. Among the current SNN architectures, the Liquid State Machine (LSM), a form of Reservoir Computing (RC), stands out due to its low resource utilization and straightforward training process. In this paper, we present a custom memristor-based LSM circuit design with an online learning methodology. The proposed circuit implementing the LSM is designed using SPICE to ensure precise device level accuracy. Furthermore, we explore liquid connectivity tuning to facilitate a real-time and efficient design process. To assess the performance of our system, we evaluate it on multiple datasets, including MNIST, TI-46 spoken digits, acoustic drone recordings, and musical MIDI files. Our results demonstrate comparable accuracy while achieving significant power and energy savings when compared to existing LSM accelerators. Moreover, our design exhibits resilience in the presence of noise and neuron misfires. These findings highlight the potential of a memristor based LSM architecture to rival purely CMOS-based LSM implementations, offering robust and energy-efficient neuromorphic computing capabilities with memristive SNNs.

Spiking neural networks have become an important family of neuron-based models that sidestep many of the key limitations facing modern-day backpropagation-trained deep networks, including their high energy inefficiency and long-criticized biological implausibility. In this work, we design and investigate a proof-of-concept instantiation of contrastive-signal-dependent plasticity (CSDP), a neuromorphic form of forward-forward-based, backpropagation-free learning. Our experimental simulations demonstrate that a hardware implementation of CSDP is capable of learning simple logic functions without the need to resort to complex gradient calculations.

Multimedia applications for machine learning mod-els are characterized by the fusion of multiple modalities of data. In this work, we highlight the trust and robustness challenges of machine learning that arises from data fusion. To do so, we present three case studies demonstrating how multimedia applications exacerbate existing challenges of trustworthy and robust machine learning. For the first case study, we investigate the impact of fusion depth on the robustness of multi-modal machine learning models, observing that model architecture could impact robustness. For the second case study, we investigate the impact of fusion modality on the robustness of multi-modal machine learning models, observing that fusion models are only as robust as their most susceptible modality. For the third case study, we explore the impact of weight quantization techniques on the robustness of multi-modal models, observing the need for modality-based quantization schemes. Through these case studies, we hope to shed light on the unique trust and security challenges that arise in machine learning models when applied in multimedia applications and offer insights to fortify such systems in real-world scenarios.