We propose a novel digital-to-analog converter (DAC) weighting architecture that statistically minimizes the distortion caused by random timing mismatches among current sources. To decode the DAC input codewords into corresponding DAC switches, we present three algorithms with varying computational complexities. We perform high-level Matlab simulations to illustrate the dynamic performance improvement over the segmented structure.
A mixed-signal hardware accelerator for solving a modern Hopfield network (MHN) is presented. Unlike classical Hopfield networks (CHNs), MHNs offer significantly higher storage capacities while requiring fewer updates to reach a solution. The proposed accelerator integrates digital storage and binary computation with analog current-mode processing to implement the exponential interaction functions essential for the strong nonlinearity characteristic of MHNs. Designed in TSMC 65nm CMOS technology, the network consists of eight 8-bit binary neurons. Circuit simulations across 256 input combinations demonstrate that, when prompted with an input, the eight-neuron network converges to one of eight stored patterns within two asynchronous update cycles, taking 1.08 ms. Of all inputs, 91% are transformed into either the closest or second-closest stored pattern, as measured by Hamming distance. Supplied by a single 1V supply, the accelerator consumes $63.3 \mu \mathrm{W}$, which makes it the most power-efficient solution among CHN or CHN-based associative memory hardware accelerators compared. Achieving eight pattern storage using only eight neurons, the proposed accelerator demonstrates the significant efficiency of MHNs in terms of patterns stored per neuron in an energy-efficient manner.
This paper discusses alternative implementations of radio-frequency (RF) analog-to-digital converters (ADCs) by using bandpass delta-sigma modulators $(\text{BP}-\Delta\Sigma \text{Ms})$. Main architectural strategies, including loop-filter order, quantizer resolution, notch-frequency position, undersampling, and feedback digital-to-analog converter (DAC), are overviewed while considering their practical limitations in terms of system complexity, stability, dynamics, and power consumption. Additionally, the combination of tunable notch-frequency and bandpass finite impulse response (FIR) filtered DAC is discussed as an efficient approach, offering reduced sensitivity to nonlinearities and clock jitter compared to the prior art1.
This paper explores a trajectory-based local navigator for mobile robots in which system identification is used to identify a kinodynamic model that generates trajectories capturing vehicle drivability constraints. A physics-based differential-drive model produces the ground-truth dataset which in combination with velocity command sequences inform an Auto-Regressive eXogenous input (ARX) system framework. Experimental evaluations are conducted across diverse driving scenarios and vehicle loading conditions, incorporating both training and validation datasets. The identified models demonstrate strong predictive capability, with the resulting trajectories closely matching groundtruth paths and validating the effectiveness of the proposed approach.
An automated design methodology for RF circuits using a feedforward neural network is presented in this paper. Machine learning techniques for circuit design automation require a large amount of data for training. Generation of such large dataset from RF circuit simulation is very time consuming and computationally expensive. The proposed technique uses transfer learning in a two step approach which significantly reduces the amount of data needed from SPICE level circuit simulations. A large dataset, generated from the analytical models, is used in the initial training and a much smaller dataset, generated from the SPICE simulations, is used for transfer learning. The proposed technique is demonstrated through automated design of RF oscillators and very high accuracy is obtained in achieving the target specifications.
This paper presents an integrated current mode feature extraction system. The system includes a sign bit generator, an integrator, a peak detector, a pulsewidth determiner, and a digital signal generator. The feature extractor was verified through simulations for a SiPM output signal up to 2.86 MHz. The system had an overall power consumption of $550 \mu \mathrm{W}$.
Due to minute discrepancies in process conditions, material properties, and geometrical defects, all CMOS devices have statistical variations in electrical characteristics. These unwanted variations carry features unique to a given process and cannot be imitated. In particular, native traps at interfaces of semiconductors and defects in thin-film devices can be used to enhance hardware security at the chip level. Such traps and defects, and their energetic distributions, can be probed on-chip by pulsed I-V characterization step that can generate a unique transient response with identifiable features. Trap properties extracted from such native or engineered current transients can be used to establish new forms of process identification and reliability monitors. In this paper, we propose to use pulsed current spectroscopy (CTS) technique and a proven Bayesian deconvolution approach that can efficiently capture trap properties to monitor such tamper-resistant digital 'fingerprints' for process identification and chip reliability. A proof-of-concept study based on simulated MOSFET drain transients is also presented to verify its practical use in CMOS devices. The proposed CTS approach can be used to enhance hardware security by superior process identification, avoiding supply-chain attacks based on suboptimal materials and counterfeiting of critical circuit elements via short-term ($\sim \mu$ s to second) current transients. It can also be used to monitor overall chip reliability, thanks to the long-term episodic comparisons of trap generation and evolution.
Dual-output look-up tables (LUTs) are supported by modern commercial Field-Programmable Gate Array (FPGA) architectures. Existing technology mapping usually generates dual-output LUTs by merging single-output LUTs. However, these mapping solutions often fail to fully leverage the dual-output capability. This paper introduces a novel FPGA mapping scheme for dual-output look-up tables (LUT), designed to improve synthesis performance significantly. By introducing new metrics functions, kl-cut generation method, and methods to add secondary LUT outputs, the proposed approach enables thorough exploration of the design space. Synthesis results show that the proposed method achieves $\mathbf{3 0. 2 \%}$ and $\mathbf{3 2. 0 \%}$ improvement in LUT usage and depth when mapping dual-output LUTs, outperforming leading-edge mapping tools.
The inherent functional behavior of reconfigurable field effect transistors (RFETs) is applied to different topologies of operational amplifiers. This leads to op-amps with unique abilities. By switching the internal bias voltages, the proposed op-amps can still perform even if the supply voltage is inverted. Furthermore, we demonstrate that the tunability of RFETs allows for parameter adjustment at runtime. In that manner, the op-amp can be optimized for specific performance characteristics, such as higher DC-gain or GBW. The developed floating biasing circuit for the differential pair based on RFETs enables utilization of the full reconfigurability that would not be possible with regular CMOS devices.
Phase noise is a key factor affecting the shortterm stability of clocks, specifically for low power designs. To address the need for low-cost, low-SWaP (size, weight, and power) micro-electromechanical system (MEMS)-based clocks in wearable/military applications while enhancing short-term stability, we present a $4.33 ~\text{mW}, 64.5 \text{MHz}$ tunable-gain multistage trans-impedance amplifier (TIA)-based oscillator in 65 nm CMOS. Integrated within a closed-loop system with a piezoelectrically transduced shear-BAW resonator, the proposed CMOS TIA design achieves phase noise of $\mathbf{- 1 1 8. 2 ~ d B c / H z}$ @ $\mathbf{1 K H z}$ offset frequency, a noise floor of $\mathbf{- 1 5 8. 2 ~ d B c / H z}$, 205.1dB FOM @ 1 KHz offset, and an exceptional $\mathrm{f}_{\text {res }} \times \mathrm{Q}$ product exceeding 1014, demonstrating significant performance improvements in shortterm stability of CMOS-MEMS oscillators.
Medical image segmentation is crucial for computeraided diagnosis, yet traditional deep learning models often fail to generalize across different domains due to variations in acquisition settings. We propose a source-free, integrated novel continual learning scheme for domain-incremental medical image segmentation. Our scheme consists of three different steps that use U-Net to train on a source domain in the first step, evaluate zeroshot performance on a target domain in the second step, and reevaluate on the source to assess forgetting in the third step. Without accessing prior data during adaptation, our method remains privacy-preserving and scalable. Experiments show high performance on the source domain, competitive results on the target domain, and minimal forgetting. The performances are measured in terms of dice score, Hausdorff distance (HD), and average symmetric surface distance (ASSD). Compared to the state-of-the-art, our approach balances generalization and retention, showing robustness under domain shifts. Our proposed work establishes a reproducible and clinically practical benchmark using continual learning in segmentation.
This paper introduces a model for leakage currents in linear integrated charge pumps, along with the corresponding design procedure. The model accounts for leakage in both capacitors and switches, and it analyzes its effect on the circuit parameters such as conversion ratio, power density, and conversion efficiency. Various design trade-offs emerge when selecting different devices within a given fabrication technology, as well as when comparing different fabrication technologies. Specifically, the paper explores the performance differences between implementing the same circuit in a conventional 65-nm silicon-oxynitride polysilicon-gate process and in a $28-\text{nm}$ high-k metal-gate process. The simulation results validate the model and quantify the improvements in power density and conversion efficiency achieved in the high-k process, owing to enhanced device performance and reduced leakage currents.
The increasing integration of high-speed wireline networks in cyber-physical systems has raised critical security concerns, particularly regarding unauthorized access and control of safety-critical functionality. This work investigates physical layer authentication techniques that leverage intrinsic channel characteristics for secure, physically and spatially unique communication in high-speed broadcast networks. Specifically, we explore jitter-based fingerprinting and channel cursor adaptation as viable authentication mechanisms. Both techniques are evaluated in terms of their practicality for real-time implementation, distinguishability, and robustness to environmental variations. Simulation results demonstrate that jitter-based authentication provides overall superior uniqueness, with high distinguishability at high losses, whereas cursor adaptation performs better at low losses. The complementary nature of these approaches suggests potential benefits in their dual application in a multi-metric authentication framework.
The vulnerability of autonomous vehicle (AV) systems to Global Positioning System (GPS)-based attacks presents a significant challenge in ensuring reliable navigation and sensor integrity. This work addresses the lack of modifiable GPS data output in CARLA which limits the evaluation of sensor vulnerabilities under different attack scenarios. To overcome this limitation, we introduce a novel unbounded GPS navigation framework within the CARLA simulator. A Proportional-Integral-Derivative (PID) controller is integrated with the GPS approximation method to improve navigation performance under adversarial conditions. The framework has been tested under two GPS attack models, demonstrating its ability to handle small deviations while revealing limitations in correcting larger biases. Experimental results demonstrate successful navigation in both straight-line and waypoint-based scenarios, establishing a foundation for future work focused on mitigating sensor manipulation through reverseengineering techniques and improved GPS tracking systems.
The unique 24 GHz Doppler radar signatures of foraging honeybees were shown to resemble a linear frequency-modulated waveform. A representative signature was used as a reference waveform in a pulse compression process. Pulse compression enabled the selective detection and counting of foraging honeybees with increased sensitivity and temporal selectivity. A modified, complex Pearson correlation process implemented the digital pulse compression. This efficient technique allowed real-time processing on a 600 MHz CPU microcontroller.
In this paper, an echo-cancellation based hybrid is proposed for simultaneous-bidirectional (SBD) signaling in wireless thru-chip interface (TCI) for 3-D stacked ICs. In case of conventional unidirectional (UD) signaling, separate TCIs for transmitting and receiving data are used. Further with increase in communication distance, the inductor diameter should be increased to maintain the coupling coefficient which increases the quality factor and induces ringing. As a result, the UD signaling limits the data-rate per unit area for a given communication distance. The proposed transceiver incorporates SBD signaling by using a hybrid topology to extract the received signal by cancelling the transmitted signal in the TCI. By this approach the data-rate per unit area has increased by $\mathbf{1 0} \%$ for $\mathbf{1 e}-\mathbf{9}$ biterror rate with sampling jitter of 5 ps. The architecture has been implemented using TSMC PDK in 65 nm technology for a communication distance of $\mathbf{2 5} \mu \mathbf{~ m}$. It achieves a SBD data-rate of $20 ~\text{Gb} / \mathrm{s}$ with an energy-efficiency $1.75 \text{pJ} / \mathrm{b}$.
Biosensor innovation is advancing, yet structured, data-driven patent analysis remains limited. We introduce an API-driven retrieval and classification framework, leveraging the PatentsView API to collect and categorize 138 biosensor patents since 2019. A keyword-based classification scheme and network and trend analysis identify key technological domains, innovation trajectories, and collaboration networks. Findings show leading contributions from Illumina, Inc., IBM, and Duke University. Patent filings declined in 2021 due to pandemicrelated disruptions but rebounded from 2022 to 2024, indicating renewed research efforts. Faster patent grant timelines suggest an accelerating innovation cycle, with AI-driven biosensing, wearable monitoring, and biocompatible materials emerging as key trends. However, commercialization challenges persist for graphene-based and nucleic acid biosensors. This study provides a scalable, replicable methodology with open-source code and visual analytics, enabling automated patent retrieval, computational analysis, and interactive visualization for future research.
Heart disease is one of the major causes of mortality worldwide and in USA. Heart sound signals recorded as phonocardiogram (PCG) provide valuable insights into cardiac health. This work presents a solution for monitoring user cardiac health and detecting abnormalities from PCG using artificial intelligence (AI) embedded into wearable for on-device monitoring. To meet the power and area constraints in wearable sensors, reservoircomputing is used as the AI module. An analog reservoircomputer (RC) test-chip fabricated in 28nm consumes 23.5nJ while detecting heart abnormalities with 88.2% accuracy.
Traditional computing architectures struggle to keep up with modern neural networks due to energy consumption and processing speed limitations. To address these challenges, we propose MAKAN, a framework that integrates Kolmogorov-Arnold Networks (KANs) with the BITLITE memristor-based computing platform. KANs, which use learnable activation functions on edges instead of fixed functions on nodes, offer superior flexibility and accuracy, but their reliance on spline-based functions limits scalability. MAKAN overcomes this by using hat functions for piecewise linear (PWL) function approximation, efficiently implemented on BITLITE's bit-wise memristor crossbars for matrix-vector multiplication (MVM). By employing machine learning to reconstruct KAN's spline functions with PWL on memristor circuits, MAKAN significantly reduces computational overhead while preserving accuracy and interpretability. This integration results in notable improvements in energy efficiency and processing speed, making advanced neural networks more scalable and practical for real-world applications, paving the way for future advancements in energy-efficient machine learning systems.
Mobile phone processors have emerged as a key driving force in the evolution of embedded systems, thanks to their versatility, power efficiency, and cost-effectiveness. Low-cost platforms like the Raspberry Pi family are equipped with high-performance multi-core CPUs and GPUs, making them well-suited for real-time image processing tasks. This paper introduces a GPU shader method for detecting moving objects and measuring their speed using a constant-rate series of sequential images, such as live video feeds or recordings from existing traffic cameras. The system employs the industry-standard, non-vendor-specific OpenGL ES on affordable embedded systems. The CPU manages data flow to the GPU shaders, which identifies changes in pixels across frames to detect potential moving objects. The displacement of each object is then calculated, mapped into a practical distance, and returned to the CPU. This approach was implemented on a low-cost Raspberry Pi 4, successfully extracting speed data from 720p video at 10 FPS. Additionally, the code is easily portable to newer, faster embedded platforms, enabling even higher data rates.
