The breakdown distribution of a magnetic tunnel junction (MTJ) with an ultrathin (∼1.2 nm) MgO barrier was studied, and two distinct distributions were identified. The breakdown distribution with high value demonstrates a wide peak-to-peak separation (∼13.4σ) to the critical spin torque induced switching voltage. However, the peak-to-peak separation is only ∼8.4σ for the devices showing low breakdown value. Both abrupt and gradual breakdown events were observed in two distributions. The dependence of the percentage of low breakdown devices as a function of bias polarity, test and stress conditions, MTJ film properties, and process conditions was investigated. The low breakdown percentage can be significantly reduced by increasing the RA value and MTJ process optimization.

In some cases such as junctions with low magnetic thermal activation energy, the magnetization of the free layer in MgO-based magnetic tunnel junctions (MTJs) can back hop to its original direction after successful spin torque induced switching. The back-hopping is observed in both current directions corresponding to parallel-to-antiparallel and antiparallel-to-parallel switchings. For bias voltage pulses with increasing pulse width, the threshold voltage for back-hopping appears to decrease together with spin-torque switching and junction breakdown thresholds, but its rate of decrease is less. Increasing the anisotropy field Hk by increasing the MTJ aspect ratio can raise the threshold voltage of back-hopping significantly.

We have demonstrated a robust magnetic tunnel junction (MTJ) with a resistance-area product RA=8 Omega-mu m(2) that simultaneously satisfies the statistical requirements of high tunneling magnetoresistance TMR > 15 sigma(R-p), write threshold spread sigma(Vw)/< Vw > <7.1%, breakdown-to-write voltage margin over 0.5V, read-induced disturbance rate below 10(-9), and sufficient write endurance, and is free of unwanted write-induced magnetic reversal. The statistics suggest that a 64Mb chip at the 90-nm node is feasible.

A novel orthogonal wiggle cell for either adjacent-reference architecture or self-reference architecture is proposed to enhance the read/write operation of MRAM. With reliability and non-disturbance of the device being verified, the mass production of MRAM is feasible because of the stabilized functionality and improved performance

A positive bias temperature instability (PBTI) recovery transient technique is presented to investigate trap properties in HfSiON as high-k gate dielectric in nMOSFETs. Both large and small-area nMOSFETs are characterized. In a large-area device, the post-PBTI drain current exhibits a recovery transient and follows logarithmic time dependence. In a small-area device, individual trapped electron emission from HfSiON gate dielectric, which is manifested by a staircase-like drain current evolution with time, is observed during recovery. By measuring the temperature and gate voltage dependence of trapped electron emission times, the physical mechanism for PBTI recovery is developed. An analytical model based on thermally assisted tunneling can successfully reproduce measured transient characteristics. In addition, HfSiON trap properties, such as trap density and activation energy, are characterized by this method.

Drain current degradation in HfSiON gate dielectric nMOSFETs by positive gate bias and temperature stress is investigated by using a fast transient measurement technique. The degradation exhibits two stages, featuring a different degradation rate and stress temperature dependence. The first-stage degradation is attributed to the charging of preexisting high-k dielectric traps and has a log(t) dependence on stress time, whereas the second-stage degradation is mainly caused by new high-k trap creation. The high-k trap growth rate is characterized by two techniques, namely 1) a recovery transient technique and 2) a charge-pumping technique. Finally, the effect of processing on high-k trap growth is evaluated.

The switching behaviors in elliptic shaped (aspect ratio=2) submicron magnetic tunnel junctions using CoFeB single free layer and CoFeB∕Ru∕CoFeB synthetic antiferromagnetic (SAF) free layers are studied. It is found that under considerable stray fields originating from pinned layers, junctions with single free layer show complex switching behaviors with larger Hc variations. In contrast, junctions with SAF free layers exhibit kink-free R-H loops and less Hc variations. The Hc of junctions with SAF free layers is less dependent on the junction size than that with a single free layer. Furthermore, for junctions smaller than a critical size the SAF free layers have a smaller Hc than single free layers.

MRAM structures based on 1T2UMTJ cell and PWWL architecture are proposed to shrink the bit size with a potential down to 6 F/sup 2/ by a so-called ExtVia process and reduce the writing current by a factor of two, combined with the nature of non-volatility and high speed, making the MRAM suitable for universal memory applications.

The crystallization structure and thickness of PtMn layer in a magnetic tunnel junction system are important factors to improve its exchange bias effect. This study shows that the PtMn layer could be changed from a FCC (111) structure to a FCT (111) structure after annealing above 270 degreesC. The minimum thickness of PtMn layer is found to be 10 nm for exchange coupling effect to be occurred in our MTJ system. The magnetic exchange effect between PtMn and SAF layers is near 4,300 Oe. Annealing temperatures can be higher than 400 degreesC for samples without patterning; however, temperature at 275 degreesC is too high for samples after patterning. This may be due to the breakdown of edges of the patterned samples as well as the complicated environments around the patterned samples. (C) 2004 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Accelerated scaling of CMOS technology has contributed to remove otherwise fundamental barriers preempting its widespread application to mixed-signal/radio-frequency (MS/RF) segments. Improvements in device speed, matching, and minimum noise figure are all consistent with fundamental scaling trends. Other figures-of-merit such as linearity and 1/f noise do not scale favorably but are not considered to be roadblocks when viewed from a circuit design perspective. Furthermore, interconnect architectural scaling trends in logic technology have facilitated improvements in passive-component performance metrics. These improvements compounded with innovations in circuit design have made CMOS technology the primary choice for cost driven MS/RF applications. This paper reviews active and passive elements of CMOS MS/RF system-on-chip (SoC) technology from scaling perspective. The paper also discusses the implications that physical phenomena such as mechanical stress and gate leakage as well as gate patterning have on technology definition and characterization.

Proton bombardment technology is integrated into the standard IC process as a post-backend process module to form local semi-insulating regions on mixed-signal/RF chips. With 10/sup 15/ cm/sup -2/, 100 /spl mu/m deep bombardment through mask windows, /spl rho//sub s/=20k/spl sim/50k /spl Omega/.cm regions are formed, which are thermally stable at 200/spl deg/C. High-Q inductors and reliable MOSFETs are made on same chip with no need of tuning the existing wafer process. Design rules are established.

Current foundry technology menus are so rich that they are sufficient to provide single chip solutions to a wide variety of desktop, portable and communication systems. At 130-nm and 90-nm generations, many of the device characteristics are no longer a straightforward extension of past generations. Special attention should be made for mixed-signal chip design. A judicious choice of devices and careful trade-off between version options should be made to maximize the benefit from the latest foundry offerings.

A versatile mixed-signal and RF (MS/RF) technology based on a foundry 90 nm CMOS process was demonstrated with excellent MOS transistor f/sub T/ at 160-185 GHz. Passive elements of various process schemes were fabricated for cost/performance evaluation. To realize low-cost system-on-chip (SOC), passive elements like 0.9 /spl mu/m Cu inductors and metal-stacked capacitors (MOM) were implemented using a standard logic back-end process. For high performance MS/RF solutions, inductors with 3 /spl mu/m Cu and ultra thick 6 /spl mu/m Cu top metal were fabricated to achieve high quality factors, Q>15 at 1 GHz and peak Q>20. Precision metal-sandwiched capacitors (MIM) with unit capacitances of 1.0, 1.5 and 2.0 fF//spl mu/m/sup 2/ were characterized and compared. Comparable or better matching was observed for MIM with higher unit capacitance, implying the possibility for chip size reduction. Specifically, the advantage of better MIM matching was demonstrated for the first time on the data resolution improvement of an A-to-D converter.

A novel design and performance of a power MOS transistor for RF system-on-chip applications are reported. The power MOS transistor with high breakdown voltage is integrated into 0.18-mum CMOS technology with only one additional mask. By an optimized design considering all aspects of dc and RF performances, a power MOS transistor with 16-GHz cutoff frequency and 24-GHz maximum oscillation frequency has been demonstrated. In addition, the power gain is 12 dB at 2.4 GHz with power-added efficiency of 50%. In this study, the device architectures that include drain engineering, substrate engineering, and gate scaling are investigated comprehensively.

This paper describes a novel design concept and experimental hardware data of array heads for close-packed track recording. The heads are batch fabricated on wafers in a linear fashion. These 60-turn thin-film inductive heads are designed with 6 /spl mu/m pitch helical coils and planar side-by-side P1/G/P2 yokes structure. The linear head array is placed along the upstream-to-downstream direction of the track. By skewing the array slightly off the track direction, each head of the array aligns to an individual track. In this case, the track pitch is about 5 /spl mu/m, which is the yoke height. With this head arrangement, even though a thermal expansion causes the head-to-head distance to increase along the upstream-downstream direction, it does not cause a thermal induced track misregistration problem. The increased head-to-head distance only affects the timing of signals between tracks, which can be compensated by the channel electronics. Thus, the thermal induced track misregistration problem is eliminated using this design. The guard bands between tracks are not necessary, and a close-packed track recording is possible. A state of the art head impedance of the 60-turn head is obtained: 11 /spl Omega/ and 0.40 /spl mu/H. The gap-to-gap pitch is 100 /spl mu/m. The overall head-to-head isolation is greater than 50 dB at 10 MHz. Such a large isolation is realized by suppressing the capacitive coupling between lead wires using a ground plane and grounded wall structures. The tight winding of the helical coils reduces the magnetic coupling between the heads.

This article describes novel array heads for close packed track recording. The heads are batch fabricated on wafers in a linear fashion (Fig. 1). These 60-turn thin-film inductive heads are designed with 6 μm pitch helical coils and planar side-by-side P1/G/P2 yoke structures. The linear head array is placed along the upstream-to-downstream direction of the track. By skewing the array slightly off the track direction, each head of the array aligns to an individual track (Fig. 2). In this case, the track pitch is about 5 μm, which is the yoke height. With this head arrangement, even though thermal expansion causes the head-to-head distance to increase along the upstream–downstream direction, it does not cause a thermally induced track misregistration problem. The increased head-to-head distance only affects the timing of signals between tracks, which can be compensated by the channel electronics. Thus, the thermally induced track misregistration problem is eliminated using this design. The guardbands between tracks are not necessary and a close-packed track recording is possible. A state of the art head impedance of the 60-turn head is obtained: 11 Ω and 0.40 μH. The gap-to-gap pitch is 100 μm. The overall head-to-head isolation is greater than 50 dB at 10 MHz. Such a large isolation is realized by suppressing the capacitive coupling between lead wires using a ground plane and grounded wall structures. The tight winding of the helical coils reduces the magnetic coupling between the heads.

This paper presents the characteristics of a silicon IC process compatible, nonvolatile memory. The basic storage element is a thin-film stripe that consists of a pair of 9-nm ferromagnetic (NiFe) layers spaced with 2.2-2.5 nm of non-magnetic Cu film. The magnetization, M, of one of the layers is pinned along the longitudinal direction of the stripe with an antiferromagnetic material (FeMn), while the M of the other layer is free to rotate. This structure is known as a spin valve. When the Ms of the pair are in the same (parallel) direction, the resistance is lower than when they are in the opposite (anti-parallel) direction by 5-8%. This property is well known as the giant magneto-resistive effect. The memory cell is made up of a storage resistor stripe and the x/y select wires, typically 100 nm thick. The current pulses in the select wires generate a vector sum of magnetic field that switches the cell state. The switching field in the longitudinal direction is lowered when a transverse field is applied. The memory cells were fabricated on thermal oxide on silicon wafers. The sputter deposition and etch process of the spin valve does not affect the leakage nor does it alter the Vt of FETs, and thus may be integrated into the metallization steps of the silicon wafer processing

This paper presents the design and the characteristics of a nonvolatile memory cell using giant magneto-resistance effects. Unlike other magnetic memory cells, the present cell design exploits the full ΔR of the spin valve material. A dc voltage difference between the two cell states of 30 mV range has been realized on a cell stripe only 6-microns long, making it compatible with the high-speed sensing schemes presently employed in silicon RAMs. The cell switches states in sub-nanoseconds. Its performance/density is close to that of the static RAM cell

To evaluate the potential of scaled CMOS technologies for analog application, a very high speed analog-digital converter (ADC) was designed and fabricated using a 3.6-V, 0.8-micron and a 2.5-V, 0.5-micron digital CMOS technology. The former was designed for sampling at 200 MHz and the latter at 300 MHz worst case. This paper describes the design issues and the performance of the ADC fabricated in two generations of CMOS.