A novel silicon photodetector suitable for high-speed, low-voltage operation at 780- to 850-nm wavelengths is reported. It consists of an interdigitated p-i-n detector fabricated on a silicon-on-insulator (SOI) substrate by using a standard bipolar process. Biased at 3.5 V, this device attains a -3-dB bandwidth in excess of 1 GHz at /spl lambda/=840 nm. The dc responsivity measured at /spl lambda/=840 nm on nonoptimized structures ranges from 0.05 to 0.09 A/W, depending on the finger shadowing factor. A new approach for improving the responsivity is proposed and quantitatively analyzed. The fabricated devices exhibit extremely low dark currents, small capacitance, large dynamic range, and no evidence of low-frequency gain. The overall performance and process compatibility of these photodetectors make them viable candidates for the fabrication of silicon monolithic receivers for fiber-optic data links.

An advanced 0.1 mu m CMOS technology on SOI is presented, In order to minimize short channel effects, relatively thick nondepleted (0.15 mu m) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 mu m were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI, Devices with little short channel effect all the way to below 500 Angstrom effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body, These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI = FO = 3) was 64 ps, and loaded NAND (FI = FO = 3, C-L = 0.3 pF) delay was 130 ps at supply of 1.8 V, This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained.

This paper examines the off-state leakage current of 0.25 /spl mu/m SOI devices for low-voltage and low-power applications. From both electrical measurements and two-dimension simulations (with impact ionization) the off-state leakage current is found to be due to the back gate conduction arising from the combined drain induced barrier lowering and floating body charging effects. Comparison between thin and thick buried oxides shows that the use of a thin buried oxide is limited by the presence of fixed charge density in the buried oxide, a high doping level is thus required to prevent any parasitic conduction at the back interface.<>

An advanced 0.1 /spl mu/m CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick non- delpleted (0.1 /spl mu/m) SOI film, highly non-uniforin channel doping and source-drain extension-HALO were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 /spl mu/m were obtained. Very high speeds were obtained: Unloaded delay was 20 psec, and fully loaded NAND (FI=FO=3, CL-0.3 pF) delay was 130 psec at supply of 1.8 V.

The successful application of sub-micron scaling principles to device fabrication involves an integration of tool, resist system, and process control. The precision overlay capability of a modified IBM EL-3 variable shaped beam lithography tool has been used to achieve optimized scaling of a 0.25 micrometers bipolar technology. Although the total device size is strongly coupled to linewidth control and overlay accuracy for all circuit levels, the overlay between the emitter opening and the shallow trench isolation is considered to be the most critical. We report on the integration of an advanced electron beam lithography and resist process capability with an innovative bipolar device technology to achieve emitter coupled logic (ECL) delays of 20.8 ps at a switching current of 1.1 mA. These results demonstrate the feasibility and performance leverage that can be accomplished through the aggressive scaling of conventional bipolar technologies.

In this paper a CMOs technology with the nominal channel length of 0.15 Am and minimum channel length below 0.1 /spl mu/m is presented. Loaded NAND (FI=FO=3, CL=240 fF) delay of 200 psec and unloaded delay of 33 psec at supply voltage of 1.8 V is demonstrated. In order to minimize short channel effects down to channel length below 0.1 /spl mu/m, highly non-uniform channel doping obtained by indium and antimony, and source-drain extensions were utilized. To minimze the gate RC, a polycide s stack gate structure was used.

A complementary silicon bipolar technology offering a substantial improvement in power-delay performance over conventional n-p-n-only bipolar technology is demonstrated. High-speed n-p-n and p-n-p double-polysilicon, self-aligned transistors were fabricated in a 20-mask-count integrated process using an experimental test site designed specifically for complementary bipolar applications. N-p-n and p-n-p transistors with 0.50-mum emitter widths have cutoff frequencies of 50 GHz and 13 GHz, respectively. Two novel complementary bipolar circuits-ac-coupled complementary push-pull ECL, and NTL with complementary emitter-follower-display a significant advantage in power dissipation as well as gate delay when compared to conventional n-p-n-only ECL circuits. Record power-delay products of 34 fJ (23.2 ps at 1.48 mW) and 12 fJ (19.0 ps at 0.65 mW) were achieved for these unloaded complementary circuits, respectively. These results demonstrate the feasibility and resultant performance leverage of high-speed complementary bipolar technologies.

The reduction of the bipolar device parasitic capacitances and resistances is becoming increasingly important with the dramatic improvements of the intrinsic transistor performance over the last few years. Higher circuit performance can be achieved both through use of very advanced lithography to arrive at smaller lateral dimensions [I], and improved device integration. In this paper, we present a novel bipolar isolation structure, called SPIRIT (Sequentially Planarized InteRlevel Isolation Technology), which reduces the collector-base (C CB) and collector-substrate (C CS) capacitances and the extrinsic base resistance (R BX) significantly.

Devices have been designed and fabricated in a CMOS technology with a nominal channel length of 0.15 mu m and minimum channel length below 0.1 mu m. In order to minimize short-channel effects (SCEs) down to channel lengths below 0.1 mu m, highly nonuniform channel dopings (obtained by indium and antimony channel implants) and shallow source-drain extensions/halo (by In and Sb preamorphization and low-energy As and BF/sub 2/ implant were used. Maximum high V/sub DS/ threshold rolloff was 250 mV at effective channel length of 0.06 mu m. For the minimum channel length of 0.1 mu m, the loaded (FI=FO=3, C=240 fF) and unloaded delays were 150 and 25 ps, respectively.< >

The full leverage offered by electron-beam (e-beam) lithography has been exploited in a scaled 0.25-mu-m double-polysilicon bipolar technology. Devices and circuits were fabricated using e-beam lithography for all mask levels with level-to-level overlays tighter than 0.06-mu-m. Ion implantation was used to form a sub-100-nm intrinsic base profile, and a novel in-situ doped polysilicon emitter process was used to minimize narrow emitter effects. Transistors with 0.25-mu-m emitter width have current gains above 80 and cutoff frequencies as high as 40 GHz. A record ECL gate delay of 20.8 ps at 4.82 mW has been measured together with a minimum power-delay product of 47 fJ (42.1 ps at 1.12 mW). These results demonstrate the feasibility and resultant performance leverage of aggressive scaling of conventional bipolar technologies.

A novel bipolar isolation structure with capability of significantly reducing collector-base capacitance and base resistance is presented. A silicon-on-insulator (SOI) region surrounding the collector opening is used to minimize the collector window width, and to increase the thickness of the extrinsic base contact layer for a given device topography. This partial-SOI isolation structure can be combined with any type of emitter-base self-alined bipolar transistor structure.

In this technology, first the CMOS is defined and a major part of the heat cycle is carried out. Then, the bipolar is fabricated by the rest of the CMOS. Patterned subcollector definition and epitaxial silicon growth are followed by the deep and shallow trench isolation processes. Next are the npn collector reach-through and anneal, CMOS well and threshold implants, gate oxidation and poly deposition. CMOS gate definition, reoxidation, and nMOS n/sup +/ implant. Electron-beam lithography is used to pattern the gate level in order to achieve a minimum gate poly width of 0.3 mu m. Next, the CMOS region is protected, while fabricating the bipolar. The annealing cycles for base and emitter during the process are compatible with the CMOS requirements. The minimum final emitter size is 0.5 mu m. CMOS ring oscillators with 50-ps delay per stage at 2.5-V supply, ECL ring oscillator delays of 48 ps at 1.2 mA, and fast loaded BiNMOS gate delays have been achieved.<>

A BiCMOS technology has been developed that integrates a high-performance self-aligned double-polysilicon bipolar device into an advanced 0.25 mu m CMOS process. The process sequence has been tailored to allow maximum flexibility in the bipolar device design without perturbation of the CMOS device parameters. Thus, n-p-n cutoff frequencies as high as 60 GHz were achieved while maintaining a CMOS ring oscillator delay per stage of about 54 ps at 2.5 V supply comparable to the performance in the CMOs-only technology. BiCMOS and BiNMOS circuits were also fabricated. BiNMOS circuits exhibited approximately=45% delay improvement compared to CMOS-only circuits under high load conditions at 2.5 V.< >

The fundamental limits on device performance imposed by geometrical effects are studied. Results of an extensive three-dimensional (3D) device simulation study are given and compared with experimental results of a 0.25- mu m bipolar technology. It is shown in this study that geometrical factors alone can result in lower DC current gain and lower f/sub T/ at low current densities for smaller devices. It is also shown that perimeter effects are beneficial for small emitter devices at high current densities. This is a particularly important design consideration for high current operation as in BiCMOS gates.<>

A bipolar isolation structure with the capability of significantly reducing collector-base capacitance and base resistance is presented. Partial SOI, with SOI surrounding the collector opening, can be used to reduce the collector window width in combination with any emitter-base self-aligned bipolar device structure, and in particular for device structures that feature sublithographic emitter width. Near-ideal transistor Gummel characteristics and a minimum ECL gate delay of 24 ps have been achieved with a nonoptimized lateral device layout, and simulations suggest that sub-20-ps delay at reduced switch current will be possible by using the optimized partial-SOI isolation structure.<>

An experimental 16*16, nonblocking, asynchronous crosspoint switch with 5 Gb/s channel data rate is described. Implemented in a 0.8- mu m, double-poly, self-aligned Si-bipolar ECL (emitter coupled logic) technology, the 3*3 mm/sup 2/ chip with a multiplexer-type architecture and a three-device crosspoint cell features a data path delay of 420 ps and a set-up time of 1 ns, and dissipates about 4.6 W. Signal levels are ECL compatible. This crosspoint which supports selective or full broadcasting and a simple expansion mechanism.<>

The scaling constraints on vertical profile design which are unique to liquid nitrogen temperature operation (LNT equivalent to 77 K) of ion-implanted and epitaxial Si and SiGe bipolar technologies are investigated experimentally. While conventional on-implantation techniques can yield transistors with cutoff frequencies as high as 36 GHz at LNT, these devices have limited extendibility for circuit applications due to excessive base freeze-out. A more advanced epitaxial SiGe technology can be used to simultaneously achieve an f/sub T/ for 59 GHz and superior base freeze-out properties at low temperatures, yielding a very aggressive ECL (emitter coupled logic) gate delay of 28 ps at LNT. For SiGe devices, however, the optimum collector profile design is constrained by a barrier induced at the SiGe-Si heterojunction under high injection which limits the device transconductance and f/sub T/ at LNT.<>