This work unlocks the manufacturing of nanophotonic quantum systems that exploit the unique material properties of single-crystal diamond (SCD). We achieve this by introducing a semiconductor-compatible process for the direct bonding of multiple high-quality, ultrathin diamond films onto a carrier wafer, enabling the subsequent parallel nanofabrication of optoelectronic integrated circuits. Central to this approach is a new diamond surface-preparation method that avoids boiling tri-acid mixtures while producing exceptionally clean 20 um thin single crystals. These platelets are bonded side-by-side to 100 mm silica wafers and exhibit a record shear strength of 45.1 MPa for (100)-oriented diamond, surpassing all previously reported bonding attempts. Evidence indicates that the bonding is dominated by van der Waals interactions, likely arising from mismatched protonation mechanisms between Si-OH and C-OH surface terminations, rather than from covalent-bond-driven mechanisms. Despite this non-molecular nature, the heterostructures remain stable through liquid immersions and standard nanofabrication steps. Because the method depends primarily on surface cleanliness and roughness rather than specific chemistries, it is broadly transferable across wafer materials. This capability to parallel-bond ultrathin SCD films onto large-area substrates provides a scalable route to high-performance platforms spanning nanophotonic quantum technologies, high-power electronics, MEMS, and biotechnology.

Abstract Plasmonic nanocavities enable strong light–matter interaction at room temperature through intense mode confinement, yet intrinsic optical losses impose high coupling strength thresholds to attain the strong coupling regime. We successfully address this challenge by integrating a WSe2 monolayer inside the gap of a gold nanoparticle-over-mirror(NPoM) array. The nanoparticle array excites a propagating surface plasmon polariton (SPP) at the mirror/gap interface that hybridizes with the localized surface plasmon (LSP) mode in the nanogap. While the binary LSP-WSe2 exciton interaction is relatively weak, the strong LSP-SPP coupling introduces a hybrid plasmonic mode near the exciton resonance, yielding an effective coupling constant of 2geff ≈ 218 meV, that elevates the Rabi splitting above the system dissipation threshold (145 meV). Mode dispersion and coupling are modeled numerically and studied experimentally using far-field reflectivity and near-field photoemission. Momentum-resolved hyperspectral photoluminescence measurements show anticrossing in the emission spectrum, indicating that polaritonic states decay predominantly through the radiative channels arising from the hybrid modes.

The deployment of AI on edge computing devices faces significant challenges related to energy consumption and functionality. These devices could greatly benefit from brain-inspired learning mechanisms, allowing for real-time adaptation while using low-power. In-memory computing with nanoscale resistive memories may play a crucial role in enabling the execution of AI workloads on these edge devices. In this study, we introduce voltage-dependent synaptic plasticity (VDSP) as an efficient approach for unsupervised and local learning in memristive synapses based on Hebbian principles. This method enables online learning without requiring complex pulse-shaping circuits typically necessary for spike-timing-dependent plasticity (STDP). We show how VDSP can be advantageously adapted to three types of memristive devices (TiO2, HfO2-based metal-oxide filamentary synapses, and HfZrO4-based ferroelectric tunnel junctions (FTJ)) with disctinctive switching characteristics. System-level simulations of spiking neural networks incorporating these devices were conducted to validate unsupervised learning on MNIST-based pattern recognition tasks, achieving state-of-the-art performance. The results demonstrated over 83

Heterogeneous neuromorphic hardware integrates devices with dissimilar electrical characteristics and dynamics, making functional compatibility at their interconnections a primary design challenge. Direct coupling alone is insufficient to ensure correct operation, because the load-line conditions established at each junction determine the effective operating regime. Here, we propose a junction-centered interface framework in which inter-device connections are described through assigned drive/sense roles and organized into canonical functional interface blocks. As a concrete hardware realization, a second-generation current conveyor (CCII)-based implementation is then adopted as a composite realization of these interface primitives. The framework is validated experimentally in a Pavlovian-conditioning demonstrator combining a memristive synapse with a unijunction-transistor (UJT) post-neuron. By linking local junction conditions to reusable interface functions, the proposed methodology provides a systematic basis for the design and analysis of heterogeneous neuromorphic systems.

Our work presents a scalable nanofabrication approach for diamond quantum sensors using photonic crystal nanostructures. It enhances photoluminescence efficiency while preserving spin properties, with only a moderate reduction in $\mathrm{T}_{\mathbf{2}}{ }^{*}$, achieving ${\sim} {1} \text{nT} / \sqrt{ } \text{Hz}$ sensitivity with ${6500} \times$ lower optical power than commercial systems.

Spin qubits need to operate within a very precise voltage space around charge state transitions to achieve high-fidelity gates. However, the stability diagrams that allow the identification of the desired charge states are long to acquire. Moreover, the voltage space to search for the desired charge state increases quickly with the number of qubits. Therefore, faster stability diagram acquisitions are needed to scale up a spin qubit quantum processor. Currently, most methods focus on more efficient data sampling. Our approach shows a significant speedup by combining measurement speedup and a reduction in the number of measurements needed to tune a quantum dot device. Using an autotuning algorithm based on a neural network and faster measurements by harnessing the field-programmable gate array embedded in Keysight's Quantum Engineering Toolkit, the measurement time of stability diagrams has been reduced by a factor of 9.8. This led to an acceleration factor of 2.2 for the total initialization time of a SiGe quantum dot into the single-electron regime, which is limited by the Python code execution.

We present a preliminary study on ultra-low temperature interconnections using a double-sided solid-liquid interdiffusion (SLID) process that combines solid SAC305 solder balls with liquid eutectic SnBiIn solder paste (Field's metal, Sn-16.5Bi-32.5In) on bare Cu and Ni (ENIG) metallizations. This approach enables the lowest possible reflow temperature at both the package and card levels (simulated card assembly), ensuring complete Indium homogenization due to its higher diffusivity compared to Bismuth, while achieving near-homogeneous Bismuth distribution. The study systematically optimizes SLID parameters, including solder paste volume (varied using different mask sizes), different reflow temperatures and times, to achieve complete homogenization. Experimental results show that optimal SLID conditions-140 degrees C for 5 minutes with a 700 mu m mask-ensure full Indium diffusion into SAC, while Bismuth remains near-homogeneous. To evaluate reliability, aging studies are conducted under Telcordia conditions at 85 degrees C for 500h and 1000h, analyzing interfacial and bulk microstructural evolution on Cu and interfacial evolution on Ni (ENIG). Mechanical properties by shear testing exhibit stable performance despite revealing complete Cu pad consumption. On the other hand, preliminary analyses using ENIG pad metallizations shows that Ni acts as an effective barrier to suppress Cu dissolution, thereby recommending its use to mitigate potential interfacial degradation. These findings establish the feasibility of a double-sided SLID process using SAC BGAs and SnBiIn solder for next-generation ultra low-temperature interconnections, offering superior diffusion characteristics, reduced Bi segregation, and enhanced long-term mechanical reliability compared to conventional low temperature soldering methods

This study reports new preliminary results on fully co-integrated 28 nm FD-SOI UTBB phase change memories (PCM) programmed at room temperature (RT) and cryogenic temperature (CT). The PCM is a germanium, antimony, tellurium (GST) compound type which is found to be functional at 77K with multi-state switching without additional operating requirements compared to the ambient temperature. As the phase change memory is temperature dependent, drift tests are also performed to track the change in resistance over time after programming the pulses to estimate drift coefficients. An interesting feature is that using the same programming bias conditions, the drift coefficient is three times lower at 77K with an improvement in the Ion/Ioff ratio. These results are very encouraging and open the door to the PCM in applications both at high temperatures (e.g. automotive) and at very low temperatures (e.g. space, quantum).

This paper introduces and validates a novel "Si bridge first" approach to IBM's DBHi packaging technology, which exploits the self-alignment capability of mass reflow (MR) to enable effective assembly of double-sided TSV-type Si bridges onto a substrate via solder joint surface tension. By understanding the relationship between geometry and capillary forces, we demonstrate that high-throughput MR assembly can replace thermocompression bonding (TCB). Fluidic simulations of vertical and lateral capillary forces as a function of solder thickness between metallized pillars defined optimal configurations for solder-on-pillar interconnections. A semi-additive manufacturing process supported these configurations. A design of experiments evaluated alignment effectiveness on Si bridges assembled on Si substrates. Results using a single 100 mu m diameter pillar on each bridge corner demonstrated consistent alignment accuracy under 2 mu m, achieving in some cases accuracies better than 1 mu m, while mechanical profiling showed z-tilt variations below 1 mu m. Comparisons of various corner pillar (1- 4 bumps per corner) and full matrix designs confirmed that self-alignment capability is consistent. Controlled lateral offset experiments supported the ability of the configurations to accommodate industry standard flip chip pick and place tolerances. Thermo-mechanical finite element analysis (FEM) simulations compared TSV-type Si bridges with two-sided bonding to singlesided designs, both on organic substrates in a DBHi module configuration. Results showed no significant effect on Si chip, Si bridge and substrate warpage. Si chip and underfill stresses were also equivalent. However, corner stresses in the Si bridge were significantly reduced in the two-sided bonding design due to the presence of the bottom side solder interconnections. While further experiments are necessary to validate production scaling, this study highlights the potential of MR-based solder selfalignment for TSV-type bridge assemblies with high precision and throughput, positioning it as a viable alternative to TCB.

Neural decoders for quantum error correction (QEC) rely on neural networks to classify syndromes extracted from error correction codes and find appropriate recovery operators to protect logical information against errors. Its ability to adapt to hardware noise and long-term drifts make neural decoders a promising candidate for inclusion in a fault-tolerant quantum architecture. However, given their limited scalability, it is prudent that small-scale (local) neural decoders are treated as first stages of multi-stage decoding schemes for fault-tolerant quantum computers with millions of qubits. In this case, minimizing the decoding time to match the stabilization measurements frequency and a tight co-integration with the QPUs is highly desired. Cryogenic realizations of neural decoders can not only improve the performance of higher stage decoders, but they can minimize communication delays, and alleviate wiring bottlenecks. In this work, we design and analyze a neural decoder based on an in-memory computation (IMC) architecture, where crossbar arrays of resistive memory devices are employed to both store the synaptic weights of the neural decoder and perform analog matrix-vector multiplications. In simulations supported by experimental measurements, we investigate the impact of TiOx-based memristive devices' non-idealities on decoding fidelity. We develop hardware-aware re-training methods to mitigate the fidelity loss, restoring the ideal decoder's pseudo-threshold for the distance-3 surface code. This work provides a pathway to scalable, fast, and low-power cryogenic IMC hardware for integrated fault-tolerant QEC.

This preliminary study aims to explore the feasibility of a new metal-oxide-semiconductor (MOS) device, specifically in 28-nm fully-depleted silicon-on-insulator (FD-SOI) ultra-thin body buried (UTBB) technology, with a new dedicated gate stack of magnetic material, with and without TiN metal gate, along with an gate oxide. This study focuses on stacking a magnetic material in a MOS gate through 3D HFSS numerical simulations to evaluate the magnetic field gradient under and around the MOS dot device. Typically, the polycrystalline silicon gate is replaced by a magnetic material exhibiting metallic behaviour to enable conventional electrostatic MOS control with Vg gate bias. Designed to adhere to 28-nm specifications, potential candidates for process integration are Co or Ni magnetic materials. Other materials should be selected based on the magnetic specifications and metal work function. These configurations can be used in applications with an internal or external magnetic field environment, relevant to quantum or sensor applications. Finally, 3D magnetic simulations are carried out with the HFSS tool under static conditions with electric biases.

Hybrid plasmonic systems that combine localized and propagative surface plasmons offer new opportunities for tunable light–matter interactions at the nanoscale. This paper provides the most comprehensive study to date of hybridization between gap localized surface plasmons (gap LSP) and diffraction-mediated propagative surface plasmon polaritons (SPP) in arrays of gold nanodisks over a mirror, part of the larger class of nanoparticle-over-mirror (NPoM) devices. By systematically mapping the hybrid mode dispersion as a function of array geometry over a large parameter space, we extract the coupling strength via a coupled oscillator model and reveal its dependence on key structural parameters, with gap thickness identified as the primary tuning factor. The resulting hybrid modes enhance the optical quality factor by nearly fivefold compared to classical LSP while maintaining strong near-field confinement, combining the advantages of their constituent modes. Dephasing times were measured with interferometric time-resolved photoemission electron microscopy (ITR-PEEM). Using a scalable lithography-compatible NPoM architecture that minimizes the optical index mismatch between the dielectric between the nanodisks and the gap material (Al2O3), we achieved the highest coupling strength (123 meV) and dephasing time range (23–50 fs) to date in NPoM arrays.

This study investigates the interfacial microstructural evolution and mechanical behavior of eutectic Sn58Bi/Cu and hypoeutectic Sn30Bi/Cu ball grid array (BGA) interconnections subjected to aging at 85 degrees C (Telcordia) and 125 degrees C (JEDEC). The hypoeutectic interconnection was formed using a double-sided solid-liquid interdiffusion (SLID) process combining Sn58Bi solder paste and SAC305 spheres. The microstructural analysis focused on intermetallic compound (IMC) growth, void formation, and Bi segregation. The eutectic Sn58Bi/Cu interconnection exhibited accelerated Cu3Sn growth, higher total IMC formation and significant Bi segregation at the Cu3Sn/Cu interface, resulting in extensive void formation, particularly at 125 degrees C. In contrast, the hypoeutectic Sn30Bi/Cu interconnection showed controlled IMC growth, reduced void formation, and a more stable interface. This improved microstructure is explained by the lower Bi content and the presence of Ag and Cu from the SAC sphere, both of which contribute to a more controlled Cu diffusion behavior that stabilizes IMC formation and inhibits the Kirkendall effect. To correlate the two microstructures to their resultant mechanical integrity, shear strength and fracture energy was measured on the aged interconnections before and after impact testing. The eutectic Sn58Bi/Cu interconnection exhibited a significant decline in shear strength and fracture energy after aging, especially at 125 degrees C, with cracks propagating throughout the interconnection. Subsequent impact shock testing induced both BGA detachment and further degradation in shear performance. Conversely, the hypoeutectic Sn30Bi/Cu interconnection exhibited stable mechanical integrity throughout aging and impact shock testing. These findings propose that the double-sided SAC-Sn58Bi approach to low temperature soldering affords an improved reliability over a standalone Sn58Bi interconnection.

Microelectronics packaging is evolving in complexity to become a critical enabler of cost-effective semiconductor performance scaling across the spectrum of IOT, edge and cloud computing. As such, the justified focus on semiconductor environmental impact cannot ignore the contribution from the packaging sector. This paper seeks to provide an insight into both the environmental issues at hand and the challenges and opportunities for the sustainable development of microelectronic packaging technologies, where sustainability implies balancing the issues of cost, reliability and the environment in an effort to minimize resistance to change. Several development projects are discussed from the perspective of this balanced approach. Two opportunities to reduce energy consumption in solder reflow processes are presented. The first is low temperature soldering, where a process and structure is proposed for tin-bismuth (Sn-Bi) solder that can break the paradigm between temperature reduction and reliability. The second is localized reflow, where the advantages of laser assisted bonding (LAB) are discussed and its extension to large chips demonstrated. Development activities that touch upon reducing material consumption or replacing materials with more friendly alternatives are then reviewed. Plasma de-oxidation is shown to be an effective means to replace chemical fluxes and their cleaning during solder interconnection operations. Research results on additive manufacturing using electrohydrodynamic (EHD) printing demonstrate the potential to extend this technology to the 2–3 μm line/spacing requirements of advanced packaging redistribution layers, thus becoming a more sustainable alternative to photolithography for certain applications. Finally, efforts to replace toxic, petrochemical based epoxy resins with bio-sourced alternatives are introduced, showing promising preliminary properties using isosorbide-based resins.

Spin-based semiconductor qubits hold promise for scalable quantum computing, yet they require reliable autonomous calibration procedures. This study presents an experimental demonstration of online single-dot charge autotuning using a convolutional neural network integrated into a closed-loop calibration system. The autotuning algorithm explores the gates' voltage space to localize charge transition lines, thereby isolating the one-electron regime without human intervention. This exploration leverages the model's uncertainty estimation to find the appropriate gate configuration with minimal measurements while reducing the risk of failures. In 20 experimental runs, our method achieved a success rate of 95% in locating the target electron regime, highlighting the robustness of this approach against noise and distribution shifts from the offline training set. Each tuning run lasted an average of 2 h and 9 min, primarily due to the limited speed of the current measurement. This work validates the feasibility of machine-learning-driven real-time charge autotuning for quantum dot devices, advancing the development toward the control of large qubit arrays.

Cryogenic memristor-based DC sources offer a promising avenue for in situ biasing of quantum dot arrays. In this study, we present experimental results and discuss the scaling potential for such DC sources. We first demonstrate the operation of a commercial discrete operational amplifier down to 1.2 K which is used on the DC source prototype. Then, the tunability of the memristor-based DC source is validated by performing several 250 mV-DC sweeps with a resolution of 10 mV at room temperature and at 1.2 K. Additionally, the DC source prototype exhibits a limited output drift of approximate to 1 mu V s -1 at 1.2 K. This showcases the potential of memristor-based DC sources for quantum dot biasing. Limitations in power consumption and voltage resolution using discrete components highlight the need for a fully integrated and scalable complementary metal-oxide-semiconductor-based (CMOSbased) approach. To address this, we propose to monolithically co-integrate emerging non-volatile memories (eNVMs) and 65 nm CMOS circuitry. Simulations reveal a reduction in power consumption, down to 10 mu W per DC source and in footprint. This allows for the integration of up to one million eNVM-based DC sources at the 4.2 K stage of a dilution fridge, paving the way for near term large-scale quantum computing applications.

Low conductivity of sintered nanoparticle inks/pastes is one of the major drawbacks to the adoption of inkjet-printed electronics in advanced packaging for high performance computing applications. In this work, we address this concern by exploiting selective electroless copper plating on organic substrate to further improve the conductivity of electrohydrodynamic (EHD) printed and photonically sintered silver nanoparticle interconnects. The conductivity was increased more than five times, from 2.21 x 10 MS/m to 13.66 x 10 MS/m, after 800 nm copper was plated on a printed and sintered silver test vehicle. The resulting resistivity to be about four times that of bulk copper. The printing and electroless plating parameters were optimized to fabricate local high-density interconnections to bridge two chips directly on an organic substrate coated with a dielectric. In successfully utilizing the potential of technologies like EHD jet printing, intense pulsed light (IPL) curing and electroless plating, this work aims to further the cause of establishing additive manufacturing (AM) as a competitive and sustainable solution in high-density RDL fabrication for 2.1D and 2.3D packages.

The non-ideality aspects of phase change memory (PCM) such as drift and resistance variability can pose significant obstacles in neuromorphic hardware implementations. A unique drift and variability compensation strategy is demonstrated and implemented in an FD-SOI SNN hardware unit composed of embedded phase change memories (ePCMs), current attenuators, and spiking neurons. The effect of drift and variability compensation on inference accuracy is tested on the MNIST dataset to show that our drift and variability mitigation strategy is effective in sustaining its accuracy over time. The variability is reduced by up to 5% while the drift coefficient is reduced by up to 57.8%. The drift is compensated and the SNN classification accuracy is sustained for up to 2 years with intrinsic control-free hardware that tracks the ePCM current over time and consumes less than 30 µW. The results are based on ePCM chip experimental data and pos-layout simulation of a test chip comprising the proposed circuit solution.

Seeking to circumvent conventional computing bottlenecks, hardware alternatives, from brain-inspired designs to cryogenic quantum systems, necessitate integrating emerging non-volatile memories. Yet, the immaturity and unreliability of cryogenic-compatible memories hinder scalable computing advancements. This study characterizes 28 nm FD-SOI substrate-embedded Ge-rich Ge2Sb2Te5 phase change memories (ePCMs) down to 12 K to overcome these hurdles. It reveals that ePCMs is cryogenic compatible and can encode multiple resistance states with minimal drift, essential for advanced computing solutions. Through simulations, the ePCM’s impact on a spiking neural network (SNN) performing MNIST classification is evaluated. The SNN maintains high accuracy for extended periods of 2 years at cryogenic temperatures, while an accuracy drop of 10.8% is observed at room temperature. These results highlight the potential of multilevel ePCMs in brain-inspired cryogenic computing applications, offering a promising avenue for the evolution of unconventional computing systems.