The fluctuation of circuit pressure parameters may reflect the severity of circuit clotting, but it is unclear yet which one has the highest precision for the prediction of filter clotting. Increased filter pressure drop (FPD) and transmembrane pressure (TMP) are associated with filter coagulation during continuous renal replacement therapy (CRRT). They are affected by blood flow velocity and ultrafiltration rate, which can lead to false coagulation alarms. To eliminate these effects, we proposed two parameters: blood flow resistance (BFR) and transmembrane flow Resistance (TFR), and explored their role in predicting filter clotting. We conducted a retrospective analysis of patients who underwent CRRT at Jinling Hospital between March and June 2025, and experienced at least one filter change due to clotting during CRRT. CRRT modes included continuous veno-venous hemofiltration (CVVH) and hemodialysis (CVVHD). The records of continuously monitored circuit pressure parameters were extracted. The calculated parameters, including filter pressure drop (FPD), blood flow rate-adjusted FPD(blood flow resistance, BFR), transmembrane pressure (TMP), and ultrafiltration rate-adjusted TMP(transmembrane flow resistance, TFR), were further analyzed for the association of their changes with filter clotting. To verify the necessity of adjusting FPD by blood flow rate and TMP by ultrafiltration rate, a prospective study was conducted to investigate the effect of variations in blood flow rate and ultrafiltration rate on 4 pressure parameters by intentionally stepwise modulating flow rate during the start period of the CRRT session. A total of 96 CRRT circuits (76 CVVHD and 20 CVVH) from 51 patients were included. In CVVHD mode, the efficacy of ΔBFR and ΔFPD was significantly higher than that of ΔTFR and ΔTMP (all p < 0.001) for the prediction of 1-hour later clotting. AUC of ΔBFR was bigger than that of ΔFPD, although non-significant. In CVVH mode, the AUC of ΔTFR and ΔTMP was bigger than that of ΔBFR and ΔFPD, although non-significantly (all p > 0.05). A Combination of ΔBFR and ΔTFR by the parallel rule (positive if ΔBFR > 0.075 mmHg/(ml/min) or ΔTFR > 0.115 mmHg/(ml/h)) had yielded a sensitivity of 77.1% and a specificity of 62.9% for the prediction of 1-hour later filter clotting irrespective of CRRT mode. The prospective part of the study showed that FPD was blood flow rate-dependent but not BFR, and TMP was ultrafiltration rate-dependent but not TFR. BFR (Blood flow rate-adjusted FPD) and TFR (ultrafiltration rate-adjusted TMP) are potential predictors of filter clotting, warranting further studies to verify their value.

The dual-channel multi-mode 850 nm optical Miniature Transmitter (MTx) is developed for data transmission of the ATLAS LAr calorimeter readout at LHC. The MTx’s are exposed to the radiation field of proton–proton collisions, therefore, the tolerance in Total Ionizing Dose (TID) is required. The TID effects in the MTx are investigated with X-rays and Co-60 gamma-rays for the active components of VCSEL diodes, and the customized Link-on-Chip laser driver (LOCld) developed in 0.25μm Silicon-on-Sapphire CMOS technology. The irradiation tests were conducted at various dose rates. The responses to TID are observed with degradation of laser currents at initial dose of 10 to 100 Gy(SiO2), and partial recovery with additional TID to a stable output about 90% of the original. The optical eye diagrams of irradiated samples show slightly increased jittering, and are suitable for the ATLAS requirement of 5 Gbps applications.

Abstract The study of the outcomes of critically ill patients has been a hard stuff in the field of intensive care. To explore the relationship between changes of severity scores, bioelectrical impedance analysis (BIA) and outcomes of critically ill patients, we enrolled patients (n = 206) admitted to intensive care unit (ICU) in Jinling Hospital from 2018 to 2021 with records of BIA on the days 1- and 3- ICU. Collected BIA and clinical data including simplified acute physiology score II (SAPS II) and sequential organ failure assessment. According to the baseline and change of severity scores or phase angle (PA) values, the patients were divided into: G–G, baseline good status, 3rd day unchanged; G–B, baseline good status, 3rd day deteriorated; B–G, baseline bad status, 3rd day improved; and B–B, baseline bad status, 3rd day unchanged. According to PA, the mortality of group G–G was 8.6%, and it was greater than 50% in group B–B for severity scores. The new score combining PA and severity scores established. Multivariate logistic regression analysis revealed that PA–SAPS II score was the only independent factor for 90-day mortality (P < 0.05). A linear correlation was found between mortality and PA–SAPS II score (prediction equation: $$Y(\%)=16.97\times X-9.67$$ Y ( % ) = 16.97 × X - 9.67 , R2 = 0.96, P < 0.05).

The Endcap Timing ReadOut Chip (ETROC) for the Compact Muon Solenoid (CMS) Minimum ionizing particle Timing Detector (MTD) is designed to process Low Gain Avalanche Diode (LGAD) signals with a time resolution of 40-50ps per hit, with 30-35 ps per charged particle using twolayer detector. The ETROC2, is the first full size (16 x 16 pixels) and full functionally design that has been tested in hadron and electron beams at CERN and DESY (Sep 2023 - Aug 2024). Precision timing studies at these test beams are done using a self-referential beam telescope composed of up to 4 layers/chips. This talk describes the ETROC2 beam telescope and summarizes the performance of the ETROC2 chips bump-bonded to (16x16) Fondazione Bruno Kessler (FBK) and Hamamatsu Photonics K.K. (HPK) LGAD sensors using results from recent test beams. The experiences and lessons learned during these test beams are also detailed in this talk.

The MUX64 ASIC is a 64 -to -1 analog multiplexer to accommodate 64 inputs, with one addressed to output for ADC readout. It is developed for monitoring of the Low -Gain Avalanche Detectors (LGAD) detector modules in the High Granularity Timing Detector (HGTD) of the ATLAS Phase -II upgrade. The MUX64 chips will be used in the radiation field of high -luminosity pp collisions at LHC to an integrated luminosity of 4000 fb-1. This work presents the radiation tolerance study for the MUX64 being tested with 80 MeV protons and X-ray exposures for damages caused by Non -Ionizing Energy Loss (NIEL) and Total Ionizing Dose (TID), respectively. The irradiated samples demonstrated tolerance to the NIEL to a fluence of 3.21x1015 (Si, 1 MeV) neq/cm2, and the TID of 7.46x105 Gy (Si).

Low-Gain Avalanche Detectors (LGADs) are integral to modern high-energy physics experiments, but as the number of detector elements or pixels increases, there is a growing need for power-efficient read-out circuits. Addressing this, a novel CMOS discriminator called the Pseudo Thyristor, consuming zero static current, was proposed. Leveraging this innovation, we introduce a low-power analog read-out circuit tailored for precision timing detector applications for particle physics and nuclear physics experiments. The circuit begins with a low-impedance, high-slew-rate transimpedance amplifier to capture the input signal, which is then converted to current and further amplified by a discrimination input stage before being injected into the Pseudo Thyristor. The timing information of the particle hit event is derived from its flipping time. Schematic simulation results validate the effective detection of hit events. In addition, 27% power consumption is saved compared to the traditional readout circuit. This work will be implemented in the layout and fabricated in TSMC65nm process, and measurement results will be presented in the future. This development provides a power-efficient solution for future high-energy physics read-out Application-Specific Integrated Circuits (ASICs).

A very low power discriminator circuit for pixelized detectors, called the Pseudo-Thyristor is described in this document. It is a positive feedback topology using regular PMOS and NMOS field-effect transistors (FET's) with zero static current. When a small charge is injected into the circuit, it flips rapidly due to the positive feedback and outputs a logic transition for further digitization. Simulation shows that in a 65 nm process, it is possible to achieve a detecting threshold below 5 fC while maintain the average power consumption below 10 micro -Watts when the hit occupancy is <10% for 40 MHz operation.

The Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to about 40-50ps per hit. The ETROC2 is the first full size (16x16) prototype design with the front-end based on and scaled up from the ETROC1 (4x4). The readout designs at pixel and global level and the system interfaces are all new and are compatible with the final chip specifications in terms of functionality. The ETROC2 is intended as a learning chip, as a stepstone to the ETROC3 which is intended as the pre-production design. The ETROC2 design and test results will be presented.

The ETROC2, the first full size and full functionality prototype chip for the CMS Endcap Timing Layer readout, is strategically designed to meet the SEE immunity requirements of detector operation with the low power constraint. The triplicated periphery and pixel I2C configuration registers are designed with self-correction feature. The pixel readout control is centralized in the global readout and fully triplicated. The pixel readout is not triplicated, instead protected with power-efficient one-bit correction Hamming code. The TMR protection of the on-pixel threshold calibration can be turned off allowing the detection of the beam spot during the beam test by checking the bit-flips of the internal memory cells. In the initial proton beam test in January 2024, the chip readout process did not hang throughout the tests. The Hamming code correction strategy works because the error corrected TDC data were observed in the data frames. The error-injection simulation is performed to analyze the small number of bit-flips in the configuration registers. We also performed SEE testing with a heavy ion beam in April and the data analysis is ongoing. The detailed design on the SEE immunity and the testing as well as simulation results will be presented, including follow-up SEE testing results in May and June 2024.

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signals from lpGBT before sending them to RD53B through the same cables. No Single-Event Upset (SEU) is observed in any tested channels of GBCR2 in a 400 MeV proton beam. The extrapolated bit error rate for the future HL-LHC application is below 8 x 10-16, significantly below the specified BER criterion. GBCR3 is designed to improve the immunity to single-event-upset by applying the Triple Modular Redundancy (TMR) technology to all RX channels. The retimed signals from GBCR3 have less total jitter than those from GBCR2 (35 ps versus 79 ps). Each receiver channel of GBCR3 consumes 75% more power than that of GBCR2.

We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented and verified. The emulator board is being used for the ETROC digital design verification and system development.

目的:探索慢性肾脏病(CKD)中溶质及电解质肾脏排泄分数(FEx)和肾功能的关系,比较CKD和急性肾损伤(AKI)患者FEx的差别.方法:选取2020年1月至2022年8月在国家肾脏疾病临床医学研究中心诊治的具有完整血尿生化结果的CKD或AKI患者,分析估算的肾小球滤过率(eGFR)和FEx的关系,倾向得分匹配后比较CKD和AKI中FEx的差异.结果:研究纳入261例CKD和53例AKI患者.多数FEx随CKD进展进行性升高;钠、钾、氯、磷和尿酸的排泄分数(FENa、FEK、FECl、FEP和FEUA)与eGFR密切相关,并且建立了相对排泄分数(RFE)与eGFR的回归方程.AKI患者在eGFR-FEx散点图中与CKD患者表现出大致相同的趋势.倾向得分匹配后发现eGFR≥60 mL/(min·1.73m2)和<60 mL/(min·1.73m2)时,CKD和AKI之间有显著差异的分别为尿素排泄分数(FEUN)和FEUA.FEUN<12.95％[曲线下面积(AUC)0.65,灵敏度70.0％,特异度57.1％]和FEUA>11.41％(AUC 0.74,灵敏度75.8％,特异度73.5％)分别为eGFR≥60 mL/(min·1.73m2)和<60 mL/(min·1.73m2)时诊断AKI的最佳截断值.结论:无论CKD还是AKI患者,eGFR对FEx均有显著影响,大多数FEx随eGFR降低而进行性升高.eGFR≥60 mL/(min·1.73m2)时FEUN<12.95％和eGFR<60 mL/(min·1.73m2)时FEUA>11.41％对区分CKD和AKI有诊断价值.

We present a pluggable radiation-tolerant 4-level Pulse-Amplitude-Modulation (PAM4) optical transmitter module called GBT20 (Giga-Bit Transmitter at 20 Gbps) for particle -physics experiments. GBT20 has an OSFP or firefly connector to input 16 bit data each at 1.28 Gbps. The GBT20 drives a VCSEL die with an LC lens or a VCSEL TOSA and interfaces an optical fiber with a standard LC connector. The minimum module, including the host connector, occupies 41 mm x 13 mm x 6 mm. At 20.48 Gbps, the minimum Transmitter Dispersion Eye Closure Quaternary (TDECQ) is around 0.7 dB. The power consumption is around 164 mW in the low-power mode. The SEE cross-section is below 7.5 x 10-14 cm2. No significant performance degrades after a TID of 5.4 kGy.

This talk presents a flexible self-certifying FPGA-based pixel readout test system for testing the Endcap Timing Read-Out Chip (ETROC) being developed for the CMS MIP Timing Detector (MTD). The system includes an FPGA-based emulator and a test system. The test system can take data from emulator or up to four ETROC test boards in beam telescope mode and is compatible with both ETROC1 and ETROC2 boards. A python-based GUI simplifies configuration and calibration. The system provides an efficient and reliable solution for testing ETROC chips and can be extended to other readout chips with similar architecture.

The time-to-digital-converter (TDC) using uncontrolled delay lines has a simple structure and finer measurement precision since the delay cells are pure digital gates that operate at maximum speed. For every incoming hit, two “snapshots” of the delay line are taken by the register array with two strobes separated with a known time interval. With two measurements, propagation delays of each cell in the delay line can be calibrated for the operating temperature and voltage. The two measurements can also be averaged to improve the TDC measurement precision. We will discuss various calibration approaches and present test results in this work.

A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase shifter and a fine-phase shifter to achieve a step size of 97.7 ps and an adjustable range of 25 ns. The fine delay unit is based on a Delay Locked Loop (DLL) operating at 640 MHz. The phase shifter is fabricated in a 130 nm CMOS process. The area of the phase shifter is 725 um x 248 um. The Differential Non-Linearity (DNL) and the Integral Non-Linearity (INL) are +/-0.6 LSB and +/-0.75 LSB, respectively. The jitter from -25 C to 20 C is less than 15.5 ps (RMS), including the contributions from the FPGA clock source and the PLL. The power consumption is 11.2 mW.

This paper presents the design and characterisation of a front-end prototype ASIC for the ATLAS High Granularity Timing Detector, which is planned for the High-Luminosity phase of the LHC. This prototype, called ALTIROC1, consists of a 5×5-pad matrix and contains the analog part of the single-channel readout (preamplifier, discriminator, two TDCs and SRAM). Two preamplifier architectures (transimpedance and voltage) were implemented and tested. The ASIC was characterised both alone and as a module when connected to a 5×5-pad array of LGAD sensors. In calibration measurements, the ASIC operating alone was found to satisfy the technical requirements for the project, with similar performances for both preamplifier types. In particular, the jitter was found to be 15±1 ps (35±1 ps) for an injected charge of 10 fC (4 fC). A degradation in performance was observed when the ASIC was connected to the LGAD array. This is attributed to digital couplings at the entrance of the preamplifiers. When the ASIC is connected to the LGAD array, the lowest detectable charge increased from 1.5 fC to 3.4 fC. As a consequence, the jitter increased for an injected charge of 4 fC. Despite this increase, ALTIROC1 still satisfies the maximum jitter specification (below 65 ps) for the HGTD project. This coupling issue also affects the time over threshold measurements and the time-walk correction can only be performed with transimpedance preamplifiers. Beam test measurements with a pion beam at CERN were also undertaken to evaluate the performance of the module. The best time resolution obtained using only ALTIROC TDC data was 46.3±0.7 ps for a restricted time of arrival range where the coupling issue is minimized. The residual time-walk contribution is equal to 23 ps and is the dominant electronic noise contribution to the time resolution at 15 fC.

We present the design and the performance of MUX64, a 64-to-1 analogue multiplexer ASIC for the ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one of its 64 inputs selected by six address lines for the voltages or temperatures being monitored to an lpGBT ADC channel. The prototype ASICs fabricated in TSMC 130 nm CMOS technology were prepared in wire-bonding and QFN88 packaging format. A total of 280 chips was examined for functionality and quality assurance. The accelerated aging test conducted at 85 degrees celsius shows negligible degradation over 16 days.

Background Extracorporeal blood purification therapies targeting removal of the downstream products of the inflammatory cascade in sepsis have failed to improve mortality. As an upstream process of the inflammatory cascade, activated white blood cells should be a potential therapeutic target for sepsis, and the effect of removing such cells by extracorporeal centrifugal leukocytapheresis (LCAP) is worth considering. Methods Fourteen peritonitis-induced septic pigs were randomly assigned to receive a sham operation (control group, n = 7) or one session of LCAP at 12 h after sepsis induction (treatment group, n = 7). Samples from peripheral blood at various time-points and from LCAP collection were tested. All pigs were euthanized at 48 h, and lung, kidney, liver and spleen tissues were obtained for histopathological examination. Results Two pigs died in accidents before the induction of sepsis, and 12 pigs were finally included for the statistical analysis. A significant clinical improvement was present in the treatment group relative to the control group in terms of the mean arterial blood pressure (MAP), oxygen tension (PaO 2 ), lactic acid level, oxygenation index (PaO 2 /FiO 2 ), and carbon dioxide tension (PaCO 2 , P < 0.05). Flow cytometry tests showed that a mixture of B cells, dendritic cells, T helper cells, cytotoxic T cells, monocytes and neutrophils were removed from the circulation by LCAP, resulting in sepsis-induced change trends in the control cells; these change trends were all flattened in the treatment group, although nonsignificantly. Conclusions LCAP may exert a wide-spectrum and bidirectional immunomodulatory effect on sepsis, accompanied by improvements in hemodynamics and oxygenation status.

The Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode for optimal coupling. A charge pump is implemented in one channel to provide a higher reverse bias voltage, which is especially important to mitigate radiation effects on the photodiodes. The circuit functions of QTIA successfully passed the lab tests with GaAs photodiodes.