Division, square root, and remainder are fundamental operations required by most computer systems. Floating-point and integer operations are commonly performed on separate datapaths. This paper presents the first detailed implementation of a shared recurrence unit that supports floating-point division/square root and integer division/remainder. It supports early termination and shares the normalization shifter needed for integer and subnormal inputs. Synthesis results show that shared double-precision dividers producing at least 4 bits per cycle are 9 - 18% smaller and 3 - 16% faster than separate integer and floating-point units.

This paper presents the design, verification, and synthesis results of a bit manipulation unit on a RISC-V processor. We assess area and timing tradeoffs of the additional hardware on a configurable, open-source processor. Supporting bit manipulation has no impact on the critical path of an application processor. It adds 1-2.5% to total area, or less than 1% without carry-less multiplication.

As the pace of progress that has followed Moore's law continues to diminish, it is critical that the US support Integrated Circuit (IC or chip) education and research to maintain technological innovation. Furthermore, US economic independence, security, and future international standing rely on having on-shore IC design capabilities. New devices with disparate technologies, improved design software toolchains and methodologies, and technologies to integrate heterogeneous systems will be needed to advance IC design capabilities. This will require rethinking both how we teach design to address the new complexity and how we inspire student interest in a hardware systems career path. The main recommendation of this workshop is that accessibility is the key issue. To this end, a National Chip Design Center (NCDC) should be established to further research and education by partnering academics and industry to train our future workforce. This should not be limited to R1 universities, but should also include R2, community college, minority serving institutions (MSI), and K-12 institutions to have the broadest effect. The NCDC should support the access, development, and maintenance of open design tools, tool flows, design kits, design components, and educational materials. Open-source options should be emphasized wherever possible to maximize accessibility. The NCDC should also provide access and support for chip fabrication, packaging and testing for both research and educational purposes.

Chapter 5 covers other combinational and sequential building blocks, such as adders, multipliers, and memories.

The Fast Fourier Transform (FFT) is one of the most important algorithms of the past century. It presents a way to compute the discrete Fourier transform with a computational complexity of O(N log2(N)). Its structure also provides an excellent example of the power of custom hardware accelerators. However, current tutorial-style papers implementing the FFT are not well-suited for undergraduate students since they are either too vague on important implementation details or use a pipelined architecture which can obscure important fundamental concepts of the accelerator. This paper presents a simple, single-cycle version of an FFT hardware accelerator that can be implemented on an FPGA and is accompanied with source code to easily simulate and synthesize the design available at https://doi.org/10.5281/zenodo.6219524.

This paper describes the authors’ Digital Design and Computer Architecture: RISC-V Edition textbook. The book presents a unified 1-or 2-semester course on digital design and computer architecture. We have found that learning these topics together clarifies and solidifies understanding of both concepts. The textbook begins by describing digital design concepts and techniques, from number systems, logic gates, and transistor-level gate design to synchronous sequential circuits such as finite state machines and other common digital building blocks. It then builds on these concepts to teach computer architecture and processor design by introducing the RISC-V instruction set architecture (ISA), showing how to design three RISC-V processors with limited instructions, and describing various memory organizations, including caches and virtual memory. The textbook also describes logic design using hardware description languages (HDLs), covering SystemVerilog and VHDL side-by-side. The optional appendices and online chapters introduce the C programming language, embedded system design, and practical aspects of digital design including breadboarding, ASIC design, and transmission lines.CCS CONCEPTS • Architectures • Embedded Systems • Logic

Harvey Mudd College has developed a sixth-generation circuit board with an FPGA and microcontroller for an embedded systems laboratory course. Students begin by assembling and testing their circuit board, then complete a series of laboratory projects with the chips. The course concludes with an open-ended team-based design project.

This paper describes a simplified Arm processor for VLSI education. The processor implements an 8-bit datapath and a subset of the instructions so that it fits on a 1.5 x 1.5 mm MOSIS TinyChip in an ON Semiconductor 0.6 um process. During a sequence of four labs, students learn digital integrated circuit design with commercial CAD tools from Cadence and Synopsys. The processor and cell library are provided, missing one of each interesting component for the student to design. The first lab covers leaf cell schematic and layout entry. The second generates a wordslice and adds it to the datapath. The third involves hand design of a small block of random logic for the aludecoder, and synthesis and placement and routing of the rest of the controller. The fourth lab completes chip assembly, connecting the components to the pad frame. Each lab also involves logic verification, DRC, LVS, and debug. At the end of the labs, students are prepared to define and complete an open-ended final project chip.

Researchers lacking access to suitable commercial SPICE models have widely used predictive technology models (PTMs) for simulation experiments in advanced technologies. Not all predictive models correlate well with commercial processes, leading to uncertainty about the validity of such experiments. Now that data from commercial processes are available for many nodes, this paper compares the PTM predictions against commercial processes and identifies the most realistic PTMs for bulk and multigate simulations.

Many who worked or closely observed events in West Africa during the Ebola epidemic of 2013–16 were perplexed by the uneven response of both international and national authorities but have now had many of their misgivings thoroughly discussed. Other questions, however, concerning the responses of ordinary Sierra Leoneans, Liberians and Guineans at the sharp end of the epidemic – ranging from violent resistance to self-sufficiency and innovation – have not been as satisfactorily answered. Paul Richards’ timely book shifts the emphasis to the experiences of communities, particularly in Sierra Leone, whose opinions were largely ignored during much of the outbreak by Western agencies or who were seen as ignorant and as barriers to success. One of the key advantages of the book is that it is a readable and balanced account. Richards identifies the very real challenges involved in the fight against Ebola—including the ways in which local burial practices contributed to the fast spread of the virus and how widely-advertised (but often contradictory) Western medical advice did not have the compliance rates that were envisaged. In the face of these challenges, the book tells a remarkable story of how some communities began organising their own effective and safe burial teams, quarantines, by-laws, and protective clothing. In the latter stages of the epidemic, Richards argues that communities and responders’ approaches converged, as both sides began ‘thinking like an epidemiologist and like a villager’ (p.114).

In this paper we describe how to use MIPSfpga, a soft-core MIPS processor, to teach undergraduate and masters-level computer architecture courses. The most recent release of MIPSfpga (version 2.0), consists of three packages: the MIPSfpga Getting Started Guide, MIPSfpga Labs, and MIPSfpga System on Chip. After giving an overview of these packages, we provide examples of how to integrate MIPSfpga into curricula by describing three teaching experiences that used the MIPSfpga packages: an undergraduate course at the University Complutense of Madrid, a course at the Technical University of Darmstadt, and several seminars held at various Russian research centers and universities. MIPSfpga enabled students to bridge the gaps between theoretical concepts, hands-on practice, and industrial cores by allowing them to explore, modify, and test the MIPS core and system with the support of commercial compilers and tools.

Chapter 2 addresses combinational logic , in which the outputs depend only on the current inputs. The logic gates introduced in Chapter 1 are examples of combinational logic. This chapter shows how to design circuits involving multiple gates in order to implement a relationship between inputs and outputs specified by a truth table or Boolean equation.

Chapter 4 describes hardware description languages (HDLs). HDLs are related to conventional programming languages but are used to simulate and build hardware rather than software. Most digital systems today are designed with HDLs. SystemVerilog and VHDL are the two prevalent languages, and they are covered side-by-side in this book.

Chapter 3 addresses sequential logic, in which the outputs depend on both current and past inputs. Registers are common sequential elements that remember their previous input. Finite state machines, built from registers and combinational logic, are a powerful way to build complicated systems in a systematic fashion. We also study timing of digital systems to analyze how fast the systems can operate.

This chapter introduces principles for understanding and designing complex systems. It explains that although the real world is analog, digital designers discipline themselves to use a discrete subset of possible signals. In particular, binary variables have just two states: 0 and 1, also called FALSE and TRUE or LOW and HIGH. Logic gates compute a binary output from one or more binary inputs. Logic gates are commonly built from CMOS transistors, which behave as electrically controlled switches. nMOS transistors turn ON when the gate is 1. pMOS transistors turn ON when the gate is 0.

With fabrication processes migrating from planar devices to FinFETs, the differences in physical structure necessitate evaluating the SEU mechanisms of FinFET-based circuits. Since FinFET-based bi-stable circuits have shown better stability at low supply voltages and hence improved power dissipation, it is also necessary to assess the SEU performance over a range of voltages. In this work, the SEU cross section of FinFET-based D-flip-flops was measured with alpha particles, protons, neutrons, and heavy-ions. Results show a strong exponential increase in the SEU rate with reduction in bias for low-LET particles. Technology Computer Aided Design (TCAD) simulations show that the weak variation of collected charge with supply voltage, combined with the standard bias dependence of critical charge, is responsible for this trend.