Fabrication of rapid thermal nitrided HSG transformed crown capacitor storage cells incorporating an ultrathin low pressure chemical vapor deposition (LPCVD) Ta2O5 and Si3N4/SiO2(NO) dielectric is proposed, 256 Mb array with HSG crown cells of 0.3 mu m diameter x 0.6 mu m height and 49 A T-eff showed an area enhancement factor of 1.7 (relative to untransformed crown cell), C-min/C-max ratio of >0.95, and capacitance of 16.7 fF/cell is obtained. A measured leakage current density of 0.7 nA/cm(2) at 1.2 V is reported.Metal-oxide-semiconductor capacitor (MOSCAP) devices with HSG electrode for 1 Gb application are characterized using capacitance-voltage (C-V) and current-voltage (I-V) analyses. Detailed HSG grain characterization results are presented with correlation to the electrical behavior of the devices. Devices are formed using LPCVD Ta2O5 and/or Si3N4 dielectric. HSG films formed from 4 x 10(20) atoms/cc phosphorus doped amorphous silicon show depletion in C-V behavior. It is shown that phosphine doping of HSG film is required to avoid depletion. Process selectivity of UHV/CVD HSG transformation mechanism applied to thermal oxide and nitride field dielectrics is fully explored. Selectivity limits for different types of dielectric are also presented. Effect of critical parameters such as a-Si dopant concentration, HSG incubation time, anneal conditions, and a-Si layer thickness on HSG transformation are discussed for 1 Gb crown cells.

We have developed a new fabrication process for GaAs VFET's that results in excellent performance in a 10 A prototype designed for switching in low voltage synchronous rectifier applications, The new fabrication process uses a buried carbon-doped GaAs gate structure for the gate electrodes and an epitaxial overgrowth step, We have demonstrated 10 A devices with 3.5 m of gate width and 1.5 mOhm of on-resistance (specific on-resistance of 84 mu Ohm - cm(2)), The device required a 0.5 mu m channel etched between 0.5 mu m gates placing stringent requirements on the gate side wall etch profile and epitaxial doping uniformity.

We have studied the use of tertiarybutylarsine (t-BuAsH2) for organometallic vapor phase epitaxy (OMVPE) growth of AlGaAs/GaAs heterojunction bipolar transistors (HBTs). Good dc characteristics were achieved with t-BuAsH2-grown HBT structures, including common-emitter current gains higher than 200 and 1000 for n-p-n and p-n-p structures, respectively. Near-ideal current gain dependence on the collector current density was observed, indicating that the quality of AlGaAs was suitable for high-performance HBTs. The microwave characteristics were also comparable to those of arsine-grown HBTs. These results demonstrate that t-BuAsH2 can successfully replace arsine for OMVPE growth of AlGaAs/GaAs HBT structures.

The Pd-In-Ge nonspiking Ohmic contact to n-GaAs has been investigated using the transmission line, the Kelvin, and the Cox and Strack structures. It has been found that a layered structure of Pd/In/Pd/n-GaAs with 10–20 Å of Ge imbedded in the Pd layer adjacent to the GaAs can lead to a hybrid contact. When the Ohmic formation temperature is above 550 °C, a layer of InxGa1−xAs doped with Ge is formed between the GaAs structure and the metallization. When the Ohmic formation temperature is below 550 °C, a regrown layer of GaAs also doped with Ge is formed at the metallization/GaAs interface. The contact resistivity of 2–3×10−7 Ω cm2 for this contact structure is nearly independent of the contact area from 900 to 0.2 μm2. Low-temperature Ohmic characteristics and thermal stability are also examined.

A planar heterojunction bipolar transistor (HBT) with an AlGaAs emitter layer epitaxially grown onto a selectively defined grown base layer, where the base is grown with the collector as part of the original epi, is discussed. The transistors fabricated with this process exhibit good gain and output characteristics. Transistors with 7*7 mu m/sup 2/ emitters have exhibited a DC current gain of 10 t...

The process of integrating two types of AlGaAs-GaAs emitter-down HBTs (heterojunction bipolar transistors), one with isolated emitter and one with grounded emitter, on a common n/sup +/ substrate is described. The use of a selective p/sup -/ implanted region followed by MOCVD (metalorganic chemical vapor deposition) overgrowth has resulted in junction isolation with an emitter-to-emitter blocking voltage greater than approximately 12 V. The characteristics of such integrated HBTs are examined. The advantages and limitations of the isolated emitter HBT to enhance I/O interfaces and introduce linear circuits to an all emitter-down HBT technology are addressed.<>

A process that integrates isolated-emitter heterojunction bipolar transistors (HBTs) with common-emitter HBTs in the emitter-down epi structure on n/sup +/ substrates is discussed. Overgrowth of the epi onto a p/sup -/ implanted region results in back-to-back diodes for approximately 12-V vertical isolation. Isolated transistors are used in emitter-follower output buffers for heterojunction injection logic (HI/sup 2/L) ring oscillators, demonstrating the integration of the two transistor types.< >

A planar emitter-down AlGaAs/GaAs heterojunction bipolar transistor (HBT) has been fabricated by a molecular beam epitaxy overgrowth of the n-GaAs collector on top of the base layer after the base layer was formed by beryllium implantation and rapid thermal annealing. The emitter down transistors fabricated by this process had DC current gains of 20, and ring oscillators gave a maximum switching s...

BIJFET (bipolar junction FET) technology that integrates p-channel JFETs and n-p-n HBTs (heterojunction bipolar transistors) has been developed. The devices are fabricated using epi overgrowth of an AlGaAs layer onto a GaAs layer, which simultaneously results in the emitter on the base for the n-p-n and the gate on the channel for the PJFET. The individual HBTs and PJFETs showed better stability over a wide temperature range than comparable Si devices. A prototype op amp was designed to demonstrate the capability of the BIJFET process. A measured open-loop gain of 50 dB and an open-loop gain bandwidth product of 3.6 GHz compare favorably with those of Si monolithic BIJFET op amps.<>

We demonstrate for the first time that ion implantation and implant activation annealing, combined with a heavily doped InGaAs surface layer, can be used to make nonalloying shallow ohmic contact to an n-type InGaAs (or GaAs) quantum well. Quantum Hall effect and Shubnikov–de Haas oscillations are clearly observed, which indicates that electrons in the quantum well remain two dimensional despite the post-implantation high-temperature annealing. This technique can be applied to devices that would need to make shallow ohmic contact to a thin (∼100 Å or less) quantum well, where existing selective etching approaches fail to work.

A novel process to fabricate a planar emitter-up AlGaAs-GaAs heterojunction bipolar transistor HBT, has been developed relying on selective base implantation through the emitter and the heterojunction. The selective base definition means that all three transistor contacts can be made from the top surface, thereby making device integration easier because of the planar surface topology. This simple ...

The device characteristics and circuit performance of self-aligned GaAs E/D-MESFETs have been compared. The fabrication process for both devices is discussed. Electrical measurements across a 2-in wafer showed that an average self-aligned 40- mu m-wide, 1- mu m-long enhancement device has transconductance of 275+or-17 mS/mm, an intrinsic K-value of 16.3+or-2.7 mS/V, a series resistance of 0.88+or-0.1 Omega -mm, and a threshold deviation of 28 mV. Corresponding data for the non-self-aligned devices were 191+or-19 mS/mm, 10.3+or-1.4 mS/V, 1.2+or-0.2 Omega -mm, and 45 mV, respectively. An ECL-compatible 1-kb static RAM and a 4-kb static RAM were fabricated using both self-aligned and non-self-aligned processes for comparison. Using the self-aligned process, the power consumption of the 1-kb SRAM was 230 mW, compared to 530 mW for the non-self-aligned SRAM, while access times remained the same. Typical access times for self-aligned 4-b SRAM devices ranged from a minimum of 2.8 ns to a maximum of 3.8 ns. This 1-ns range is considerably less than that of a typical non-self-aligned device with 2.5 ns of access time scatter. >

A process for Zn diffusion into GaAs during rapid thermal processing has been developed using Zn doped tungsten silicide as the diffusion source. The WSi:Zn is a sputter deposited, solid source layer that undergoes capless annealing in a quartz-halogen lamp system. For a given time and temperature the diffusion of Zn into GaAs is controlled by both the Zn concentration and the W/Si ratio in the film. Tungsten-rich films are Zn concentration “independent” while Si-rich films are Zn concentration “dependent.” Changing the film composition allows shallow Zn diffusions at either a low or a high temperature. Deep Zn diffusions are possible through higher temperatures or longer anneal times for any given WSi:Zn composition.

Neutron irradiation of Ti-6Al-2Sn-4Zr-2Mo-0.08Si (Ti-6242s) indicated that the microstructure of this alloy may be stable under irradiation, in contrast to Ti-6A1-4V (Ti-64) which showed radiation-induced phase instabilities. However, the present study showed that after 2 dpa of 9 MeV aluminum ion irradiation within the temperature range 450–700°C, Ti-6242s displayed extensive precipitation. The precipitate was identified as a bcc phase similar to that observed in Ti-64. The morphology of the precipitation response for 450–600°C was highly unusual. It consisted of the apparent agglomeration of small (~ 20 nm) precipitates into some form of array or cluster. The high temperature precipitate response (650–700°C) was normal in that the precipitate morphology was that of an elongated platelet. The unusual precipitate morphology is attributed to the observed segregation of Al and Mo to sinks. A low void density was observed between 550–650°C with the voids preferentially located near grain boundaries.

The device characteristics and circuit performance of a self-aligned and a non-self-aligned GaAs E/D-MESFETs have been compared. The fabrication process for the self-aligned MESFETs was similar to the SAINT process [1], with modifications made to enhance yield and to facilitate double-level-metal interconnection. The non-self-aligned MESFETs were fabricated with the conventional recessed-gate process. Electrical measurements across a 2-inch wafer showed that an average self-aligned, 40-µm-wide, 1-μm-long enhancement device has a transconductance of 275 ± 17 mS/mm, a K-value of 16.3 ± 2.7 mS/V, a series resistance of 0.88 ± 0.1 ohm-mm, and a threshold deviation of 28 mV. Corresponding data for the non- self-aligned devices were 191 ± 19 mS/mm, 10.3 ± 1.4 mS/V, 1.2 ± 0.2 ohm-mm, and 45 mV, respectively. A low-power-design ECL-compatible 1-kbit static RAM was fabricated. By using the self-aligned process and a higher depletion threshold, power of the SRAM was reduced from 530 mW for the non-self-aligned SRAM to 220 mW while access times remained the same.

A 2 1 / 4 Cr 1% Mo steel, heat treated to consist of upper and lower bainite and ferrite, has been shown to undergo substantial microstructural modification when irradiated with 14-MeV nickel ions at 500°C to 350 dpa at the peak damage depth. The original cementite (Fe 3 C) in upper and lower bainite was replaced by Chi phase, M 7 C 3 and M 2 C in upper bainite, and Chi and M 7 C 3 in lower bainite. The originally precipitate-free ferrite contained a significant fraction of G phase after irradiation. The replacement of Fe 3 C by M 7 C 3 and M 2 C is consistent with the fact that M 7 C 3 and M 2 C form in a quenched and tempered 2 3 / 4 Cr 1 Mo steel, but at higher tempering temperatures than does Fe 3 C. On the other hand, Chi and G phases have not been reported to occur in this steel as a result of thermal treatments. The steel is resistant to void swelling, which amounted to 0.2% or less even at the rather high dpa levels employed in this study. The quantitative data for precipitate and void number densities and sizes agree quite well with a companion neutron irradiation study of the same steel possessing an identical microstructure.

A two step rapid thermal anneal (RTA) has been studied for activating Be implanted GaAs, where a short duration, high temperature step is used to electrically activate the Be followed by a longer, low temperature anneal for lattice regrowth. p-n diodes show a substantial reduction in reverse diode leakage current after the low temperature second step anneal, when compared to a single step RTA or to furnace annealing (FA). For low energy Be implants, no difference in elecrical activiation between the two step anneal is observed. Raman studies demonstrate that residual substrate impurities and high Be concentrations inhibit restoration of single crystal lattice characteristics after RTA. Lattice quality is shown not to limit diode characteristics in the RTA material.

The dominant irradiation response of several titanium alloy systems is the production of different phases. Previous studies have shown that a thermally unstable bcc,β, phase precipitates out in the hcp matrix during irradiation. In this paper, the extent of this phase separation in Ti-6A1-4V is examined as a function of temperature for low dose ion irradiations. The alloy Ti-6A1-4V was irradiated with 9 MeV Al ions to 2 dpa at a 2 μ depth over a 500–700°C temperature range. The densities of the radiation-induced β precipitates were found to decrease at high temperatures while the size increased. The original grain boundary β phase shows no radiation effect until 650°C when it undergoes a transformation to a Widmanstätten morphology. An EDS analysis of the radiation-induced β phase indicates it is 50% higher in vanadium when compared to the thermally predicted vanadium concentration. The total fraction of bcc phase present in the irradiated region is drastically altered.

A ferritic steel (214 Cr−1 Mo) was heat-treated to produce three distinct microstructural regions; upper bainite, lower bainite and ferrite. The irradiation response of these different microstructures at 500°C to 14 MeV nickel-ion-irradiation was studied under identical conditions. Damage levels ranged from 80 dpa at the 1 μm depth to 350 dpa at the peak damage depth at 2.1 μm. Irradiated samples were studied in cross section using TEM/AEM thin foil techniques supplemented by precipitate extraction methods. The irradiation drastically changed the type of precipitate in the bainite regions from M3C carbides to radiation-enhanced M2C and M7C3 carbides, and the radiation-induced χ phase was also observed. The radiation-induced G phase was the only precipitate type formed in the initial ferrite structure. No voids were observed up to 350 dpa in any of the three microstructures unless preinjected helium was present. An average swelling of 0.2% was measured after a dose of 100 dpa in the sample preimplanted to 100 at.ppm helium.