Yield estimation is an indispensable piece of information at the onset of high-volume production of a device, as it can inform timely process and design refinements in order to achieve high yield, rapid ramp-up, and fast time-to-market. To date, yield estimation is generally performed through simulation-based methods. However, such methods are not only very time-consuming for certain circuit classes, but also limited by the accuracy of the statistical models provided in the process design kits (PDKs). In contrast, herein we introduce yield estimation solutions which rely exclusively on silicon measurements and we apply them toward predicting yield during: 1) production migration from one fabrication facility to another and 2) transition from one design generation to the next. These solutions are applicable to any circuit, regardless of PDK accuracy and transistor-level simulation complexity, and range from rather straightforward to more sophisticated ones, capable of leveraging additional sources of silicon data. Effectiveness of the proposed yield forecasting methods is evaluated using actual high-volume production data from two 65-nm RF transceiver devices.

We introduce a methodology for dynamically selecting whether to subject a wafer to a complete or a reduced probe-test flow, while ensuring that the concomitant test cost savings do not compromise test quality. The granularity of this decision is at the wafer-level and is made before the wafer reaches the probe station, based on an e-test signature which reflects how process variations have affected this particular wafer. While the proposed method may offer less flexibility than approaches that dynamically adapt the test flow on a per-die basis, its implementation is simpler and more compatible with most commonly used Automatic Test Equipment. Furthermore, unlike static test elimination approaches, whose agility is limited by the relative importance of the dropped tests, the proposed method is capable of exploring test cost reduction solutions which maintain very low test escape rates. Decisions are made by an intelligent system which maps every point in the e-test signature space to either the complete or the reduced test flow. Training of the system seeks to maximize the number of wafers subjected to the reduced flow for a given target of test escapes, thereby enabling exploration of the trade-off between test cost reduction and test quality. The proposed method is demonstrated on an industrial dataset of a few million devices from a Texas Instruments RF transceiver.

We propose a methodology for dynamically selecting an optimal probe-test flow which reduces test cost without jeopardizing test quality. The granularity of this decision is at the wafer-level and is made before the wafer reaches the probe station, based on an e-test signature which reflects how process variations have affected this particular wafer. The proposed method offers flexibility by optimizing test flow per process signature and its implementation is simple and compatible with most commonly used Automatic Test Equipment. Furthermore, unlike static test elimination approaches, whose agility is limited by the relative importance of the permanently dropped tests, the proposed method is capable of exploring test cost reduction solutions which achieve very low test escape rates. Decisions are made by an intelligent system which maps every point in the e-test signature space to the most appropriate probe-test flow. Training of the system seeks to optimize the test flow of each process signature in order to maximize test cost reduction for a given target of test escapes, thereby enabling exploration of the trade-off between test cost reduction and test quality. The proposed method is demonstrated on an industrial dataset of a million devices from a 65nm Texas Instruments RF transceiver.

Yield estimation is an indispensable piece of information at the onset of high-volume manufacturing (HVM) of a device. The increasing demand for faster time-to-market and for designs with growing quality requirements and complexity, requires a quick and successful yield estimation prior to HVM. Prior to commencing HVM, a few early silicon wafers are typically produced and subjected to thorough characterization. One of the objectives of such characterization is yield estimation with better accuracy than what pre-silicon Monte Carlo simulation may offer. In this work, we propose predicting yield of a device using information from a similar previous-generation device, which is manufactured in the same technology node and in the same fabrication facility. For this purpose, we rely on the Bayesian Model Fusion (BMF) technique. The effectiveness of the proposed methodology is evaluated using sizable industrial data from two RF devices in a 65nm technology.

We introduce a machine learning approach for distinguishing between integrated circuits fabricated in a ratified facility and circuits originating from an unknown or undesired source based on parametric measurements. Unlike earlier approaches, which seek to achieve the same objective in a general, design-independent manner, the proposed method leverages the interaction between the idiosyncrasies of the fabrication facility and a specific design, in order to create a customized fab-of-origin membership test for the circuit in question. Effectiveness of the proposed method is demonstrated using two large industrial datasets from a 65nm Texas Instruments RF transceiver manufactured in two different fabrication facilities.

We investigate the utility of correlations between e-test and probe test measurements in predicting yield. Specifically, we first examine whether statistical methods can accurately predict parametric probe test yield as a function of e-test measurements within the same fab. Then, we investigate whether the e-test profile of a destination fab, in conjunction with the e-test and probe test profiles of a source fab, suffice for accurate yield prognosis during fab-to-fab product migration. Results using an industrial dataset of ~3.5M devices from a 65nm Texas Instruments RF transceiver design fabricated in two different fabs reveal that (i) within-fab yield prediction error is in the range of a few tenths of a percentile point, and (ii) fab-to-fab yield prediction error is in the range of half a percentile point.

Yield estimation is an indispensable piece of information at the onset of high-volume production of a device. It can be used to refine the process/design in time so as to guarantee high production yield. In the case of migration of production of a specific device from a source fab to a target fab, yield estimation in the target fab can be accelerated by employing information from the source fab, assuming that the process parameter distributions in the two fabs are similar, but not necessarily the same. In this paper, we employ the Bayesian Model Fusion (BMF) technique for efficient yield prediction of a device in the target fab. BMF adopts prior knowledge from the source fab and combines it intelligently with information from a limited number of early silicon wafers from the target fab. Thus, BMF allows us to obtain quick and accurate yield estimates at the onset of production in the target fab. The proposed methodology is demonstrated on an industrial RF transceiver.

Rapid thermal processing is widely applied in self-aligned Ti silicide processes for deep-sub-micron devices. We investigated and modeled the effects of rapid thermal processing variables (silicide formation temperature and time, and anneal temperature and time) and Ti thickness on deep-sub-micron device characteristics. The effect of Ti thickness, formation temperature and time on diode leakage and bridging due to silicide lateral growth, and its correlation to silicide thickness was analyzed; as well as the effects of these and the anneal variables on n+ gate sheet resistance, silicide to source/drain contact resistance and transistor source-drain series resistance. An expression for n+ gate sheet resistance is given, as function of anneal temperature and time, silicide thickness, linewidth and TiSi2 C49 grain size after formation, based on a nucleation density model in agreement with measurements of TiSi2 C49 to C54 transformation kinetics. The tradeoffs and process window limits are discussed, as well as trends observed when scaling down lateral and vertical dimensions. We show that for advanced technologies, the scaling of silicide thickness and linewidth narrows the process window between full C49 to C54 transformation and agglomeration temperatures. Due to the high activation energy of the C49 to C54 transformation, a process window for low sheet resistance exists only for high temperature-short time processes.

A detailed kinetic study of the C49 to C54 phase transformation in TiSi2 thin films was performed, to obtain the full time, temperature, and linewidth dependence of the fraction transformed during rapid thermal annealing on patterned deep-sub-micron lines. A Johnson–Mehl–Avrami kinetic analysis showed Avrami exponents of 0.8±0.2 for all submicron lines and 1.9±0.2 for a 40 μm side square structure. The activation energy of 3.9 eV was independent of linewidth. Transformation times increased dramatically as linewidth decreased. A kinetic model based on the density of nucleation sites as a function of linewidth and C49 grain size is proposed and shown to fit the data.

The beam energy is a driving design parameter for electron beam lithography systems. To be able to compare the differences of low kV (5 kV) and high kV (100 kV) for a high-throughput system the limitations of both types of systems are evaluated. First the effect on the CD uniformity and throughput is analyzed. For any shot noise limited system the dose that is needed to obtain a required CD uniformity can be calculated. This dose depends on the total spot size and the efficiency of the electrons in the resist. For a smaller spot less dose is required than for a large spot. The current in a single beam is also determined by the spot size. A larger spot has more current. With these parameters an optimization of the required dose, spot size and single beam current can be made. It is found that although for high kV it is easier to create a small spot with a high current the low resist-exposure efficiency of the high-energy electrons limits the throughput, because the required dose is large. It is also found that for 10 wafers per hour multiple lenses or columns are required. For practical reasons (a high kV lens cannot be made as small as a low kV lens) there is a clear preference for the use of low energy in high-throughput systems. Another aspect that is crucial in the lithography process is the overlay. One of the main differences between high and low energy systems is the power that is dissipated in the wafer and the resulting error due to expansion. It is found that for both energies wafer heating is an issue, but for low kV there seem to be solutions, while for high kV the problem is 30 times bigger.

For the first time, a simple CMOS fully silicided (FUSI) process achieving n/pMOS band-edge work function was demonstrated, which is fully compatible with conventional CMOS process. Dual-work-function CMOS FUSI, with a wide range of 800 mV, was achieved by implantation of Yb into the poly of the nMOS gate (4.1-eV work function) and Ga into the poly of the pMOS gate (4.9-eV work function), respectively. The placement of the tuning elements at the metal/dielectric interface was engineered with the thermal budget, as well as the implant dose and species.

Key remaining concerns raised for implementation of Ni FUSI into manufacturing are addressed and solved suggesting that Ni FUSI is worthy for manufacturing. We studied NiSi, Ni 2 Si and Ni 31 Si 12 FUSI gates and their showing 1) Excellent reliability (NBTI, PBTI and TDDB) on HfSiON (EOT=1.1nm), with lifetimes >10 years at 1.2 V for optimized HfSiON (BTI similar/improved compared to reference MG, strong effect of N (DPN HfSiON) finding optimal point in NMOS-PMOS BTI trade-off). 2) No Ni penetration into substrate and no additional reliability degradation with multilevel metallization BEOL thermal budget. 3) Excellent mismatch characteristics and low V t variability down to L G ~40nm W-130 nm (no FUSI grain orientation effects), 4) Excellent EOT scalability with no PMOS VFB roll-off down to EOT-0.7 nm (Ni 31 Si 12 , WF-4.9 eV); 5) SRAM defectivity analysis finding main type of defects and solutions for their elimination. We also showed 6) phase formation (NiSi, Ni 31 Si 12 ) similar to blanket films at L G =30 nm.

Full/partial depletion effects are observed in n-channel FinFETs. Gate-induced floating body effect and degraded subthreshold slope are observed in partially depleted devices but not in fully depleted devices. Floating-body effects are observed in FD devices with applied negative back-gate bias.