This paper shows new insights on the stochastic nature of aging-related timing impact in digital circuits. Varying critical paths through aging trigger the need for aging compensation control loop based on an unsupervised machine learning algorithm. Adaptive Resonance Theory (ART) algorithm is favored for its ability to handle the stability-plasticity dilemma.

This work demonstrates the fundamental aspects of Mission Profile Recording as an alternative to intrusive, aging monitoring systems to cope with oxide breakdown and electromigration degradation mechanisms. A functional prototype is designed, implemented and fully tested on several wafers to achieve a full proof-of-concept. This study offers new perspectives towards product hardening and qualification with respect to an adaptive approach to real user-based workloads.

This work presents a single-supply SPARC 32b V8 microprocessor designed with Ultra Low Voltage (ULV) adapted standard cells and memories, aiming at low energy operation and stand by power. The microprocessor, equipped with 10 Transistors ULV bitcell 8KB SRAM cache, has been fabricated in Fully Depleted Silicon On Insulator (FDSOI) 28nm technology. A comparative analysis with similar implementations has been provided highlighting the performance gain and power savings that are achieved by our design methodology and implementation technology. Wafer-level tests showed that our ULV adapted microprocessor has an operating range that is functional down to 0.33V and that the ULV able cache can save from 30% to 62% energy.

This paper aims at introducing a reliable on-chip process compensation flow for industrial integrated systems. Among the integrated process compensation techniques, the main one aims at reducing the supply voltage of fast circuits in order to reduce their power consumption while maintaining the specified operating frequency. The proposed design flow includes efficient methodologies to gather/sort on-chip process data but also post-silicon tuning strategies and validation methods at both design and test steps. Concrete results are introduced in this paper to demonstrate the added value of such a methodology. More precisely, it is shown that its application leads to an overall energy reduction ranging from 10% to 20% on fast chips.