A single photon avalanche diode (SPAD) cell using N-channel extended-drain metal oxide semiconductor (N-EDMOS) is tested for its hot-carrier damage (HCD) resistance. The stressing gate-voltage (VGS) dependence is compared to hot-hole (HH) injection, positive bias temperature (PBT) instability and off-mode (VGS = 0). The goal was to check an accurate device lifetime extraction using accelerated DC to AC stressing by applying the quasi-static (QS) lifetime technique. N-EDMOS device is devoted to 3D bonding with CMOS imagers obtained by an optimized process with an effective gate-length Leff = 0.25 µm and a SiO2 gate-oxide thickness Tox = 5 nm. The operating frequency is 10 MHz at maximum supply voltage VDDmax = 5.5 V. TCAD simulations are used to determine the real voltage and timing configurations for the device in a mixed structure of the SPAD cell. AC device lifetime is obtained using worst-case DC accelerating degradation, which is transferred by QS technique to the AC waveforms applied to N-EDMOS device. This allows us to accurately obtain the AC device lifetime as a function of the delay and load for a fixed pulse shape. It shows the predominance of the high energy hot-carriers involved in the first substrate current peak during transients.

This study investigates the commonality Of TDDB under Off-state conditions across a range of CMOS nodes, from 130nm to ultra-scaled devices, i.e., 28nm FDSOI CMOS. To achieve this, Off-mode gate-oxide breakdown is analyzed under non-uniform electric field to investigate the effects of stress-induced leakage current, channel current, and lateral electric field in dielectric breakdown mechanism related to RF operations using ultra short channel devices. Oxide breakdown is characterized under DC stress with different gate-length LG as a function of drain voltage VDS and temperature. The study indicates that sub-threshold leakage current is a critical factor in determining the Off-state TDDB degradation, which is caused by a combination of band-to-band tunneling mechanism, junction current and impact ionization phenomena. The proposed Off-state TDDB compact model confirms that the leakage current is a reliable indicator of TDDB dependence precursor to hard-breakdown. Additionally, the paper discusses potential causes of the higher form factor $\beta $ value for PFET under Off-mode stressing, which may be attributed to high impact ionization, non-conducting hot-carrier effects, defect generation kinetics and a thinner defect cell size.

Off-state gate-oxide breakdown under non-uniform electric field is performed to investigate the impact of Stress-induced leakage current, channel current and lateral electric field in dielectric breakdown mechanism related to RF operations using ultra short channel devices, i.e. 28nm FDSOI MOSFET. Oxide breakdown is characterized under DC stress with different gate-length L G as a function of drain voltage V DS and temperature. Based on our proposed Off-state TDDB compact model, it has been verified that the leakage current is an accurate monitor for TDDB dependence precursor to Hard-breakdown. This paper also discusses the different possible origins of the higher form factor β value for PFET under Off mode stressing due to high impact ionization and non-conducting hot-carrier effects.

A detailed analysis of Off-state gate-oxide breakdown (BD) mode and its location under non-uniform electric field is performed in 28nm FDSOI N-MOSFET devices. We show that hard breakdown (HBD) occurs exclusively from the middle of the channel to the drain overlap extension for Off-state TDDB. HBD is characterized under DC stress with different gate-length L G as a function of drain voltage V DS and temperature. We check that the leakage current is the better monitor for TDDB dependence precursor to HBD under Off-mode stress by using the proper modeling and discussing the different possible origin of the higher form factor β value under Off mode stressing.

Hot carrier injection (HCI) is one of the more significant reliability issues in advanced CMOS technologies. If it is more and more critical in thin gate-oxides due to gate-length scaling although supply voltage is reduced, it is more problematic in thicker gate-oxide due to high voltages operation needed for input/output (I/O) devices. In this paper, we discuss important process steps from the fabrication line that may modulate HCI damage in thick gate-oxides MOSFETs dedicated to analog operation.

The huge improvements in integrated circuits manufacturing has faced great challenges between process optimization, performance requirements and the trade-off between low power operation and reliability for long term use. Both the variability at time zero and the time variability due to external constraints and aging phenomena make mandatory the validation of the CMOS technology nodes from device to circuits and products under operation. While High-K Metal-Gate (HKMG) offered good compromises down to 28nm gate-length, the move to Fully Depleted Silicon on Insulator (FDSOI) allows to further scale the dimension down to 14nm effective gate-length with ultra-thin equivalent gate-oxide thickness (EOT) of 1.35 nm. This has been obtained guarantying a small subthreshold slope for switching, small drain-induced barrier lowering (DIBL) for limited short-channel effect (SCE) and excellent current drivability thanks to a proper gate-stack with HfO2/SiON optimization and adapted rapid thermal processing and annealing. We give new insights to determine first the performance with temperature, the process variability impact at time zero and the robustness of CMOS nodes submitted to interface traps, oxide charge and recoverable traps. Their role is analysed using accelerated DC and AC experiments in devices to SRAM cell and array, focusing on the balance between hot-carrier and bias temperature damage. This allows to guaranty the technology robustness, speed performance and limited power consumption for product qualification.

N-channel Extended Drain Metal Oxide Semiconductor (EDMOS) device is analysed through its sensitivity to Hot-Carrier (HC), hot hole (HH) injections and Positive Bias Temperature (PBT) instability degradation using accelerated DC to AC lifetime technique. EDMOS device is optimized for an effective gate-length Leff = 0.25 mu m, with a gate-oxide thickness Tox = 5 nm operating at a frequency of 3 MHz at nominal supply voltage VDD = 5 V. The device is used in a mixed structure dedicated to 3D integration of Single Photon Avalanche Diode (SPAD). We show that HC reliability of EDMOS transistor can be obtained using worst-case DC accelerating degradation at high temperature transferred to the real AC waveforms applied to N-channel device placed into the SPAD cell. This allows to deduce the AC device lifetime obtained from DC stressing using a quasi-static approach consid-ering the dominant degradation mechanism at condition of maximum gate-voltage VGSmax. This is explained by the optimized structure in Tox, VDD and lateral isolation where PBT, Off mode and recovery effects have limited impacts during switching operation of the N-EDMOS device used in SPAD circuit environment.

Aging phenomena are first evidenced at device level to cell level considering a precise knowledge of the leading degradation mechanisms and interactions useful for processing optimization focusing performance vs. reliability requirements. Digital to analog circuits are then studied for product qualification based on the former results that needs specific methodologies adapted case by case with mission profile and the correlation between sensing parameter, accelerating factors for lifetime margin. This represents huge challenges for operational lifetime determination, considering top down and bottom up consistencies for relevant product qualification.

We present a detailed analysis of Off-state Time Dependent Dielectric Breakdown (TDDB) under non-uniform field performed in MOSFET devices from 28nm FDSOI, 65nm SOI to 130nm nodes. Oxide breakdown in thin gate oxide is characterized under DC stress with different gate-length LG and as function of drain voltage VDS and temperature. We show that the leakage current is a better monitor for TDDB dependence under Off-mode stress whereas a new modeling is proposed. It is found that Weibull slopes β are higher in PFET due to large amount of injected hot electrons than in NFET when hot holes are involved.

The study of parameter drift due to interface defect generation in "Off" mode or near V th is very complex, because it is often concomitant with hot hole trapping which induces turnaround effects. Improving device aging models requires to consider hot-carrier degradation (HCD) in "On/Off states", interaction of these different modes as well as any dynamic effects. The DC characterization of HCD modes might be insufficient, it is necessary to verify the quasi-static assumption made when we seek to model the degradation under realistic dynamic stress by a secession of static states. We present a detailed analysis of the interactions of HCD under "On" state and "Off" state". Pulsed stressing are used to analyze the frequency dependence of HCD and "Off-state". Such approach is required for accurate AC RF ageing modeling.

Improving device aging models requires to consider hot-carrier degradation (HCD) between On/Off modes and interaction of these different damage rate mechanisms as well as the dynamic effects. As DC characterization of HCD modes might be insufficient, it is rather necessary to check the quasi-static validity when we seek to model the degradation under realistic dynamic stress by a succession of static states. We present a detailed analysis of the interactions of HCD under On and Off state in N-FETs devices using a compact modeling based on an empirical model. Pulsed stressing by measure-stress-measure method is further used to analyze the switching time dependence of HCD and Off modes for an accurate AC RF aging modeling. This reliability methodology is useful to close the gap between the simple models used for DC HCD characterization and the degradation involved in power amplifiers under AC RF signals.

Extended Drain MOS (EDMOS) transistors were studied about hot-carrier (HC) degradation and its involvement in hard breakdown (BD) events as these smart power devices represent a big challenge to optimize under Off/On mode switching in RF circuits. N-channel devices with gate-length L G =0.5µm and two gate-oxide thicknesses were tested Tox= 2.3nm (GO1) and 8.5nm (GO2). The sensitivity to BD between Off-mode and HC is pointed out in GO1 through the hot-hole injections (HHI) that are involved as a function of gate-voltage V GS = V TH and V Gmax where the V TH case induces HC damage that can be used with series resistance increase (ΔR SD ) to detect BD events in the drift region. Hole trapping and interface traps are generated leading to the dominant effect of HHI, with very close generation rates between Off- and On- mode stressing. This can be used to prevent circuit aging giving warning level for confidence in AC lifetime for power amplifiers class E and class A.

P- and N- channel Extended Drain MOSFETs (EDMOS) are analyzed through its sensitivity to Hot-Carrier (HC) degradation using accelerated lifetime technique. N- and P- channel EDMOS are optimized for a gate-length L-G = 0.5 mu m, with gate-oxide thickness at 2.3 nm. We have evaluated more precisely the HC damage caused from channel to the extended drain by an improved extraction of series resistance (Delta R-SD) till a 2nd order mobility modeling as a function of stressing V-GS from V-GS = 0 to V-Gmax. This allows to determine the worst-case of lifetime dependence in relation to the damage in the drift zone where breakdown sensitivity is found to be intimately bound up with the hot-hole (HH) injection efficiency in N-EDMOS while P-EDMOS exhibits a larger security margin.

Hot carrier injection is one of the more significant reliability issue in advanced CMOS technologies. If it is more and more critical in thin oxides due to gate length scaling, it is also problematic in thicker oxide due to high voltages needed for I/O devices. In this paper, we show a phenomenal HCI improvement in I/O CMOS analog devices by substituting arsenic with phosphorus in channel doping for threshold voltage adjustment process.

This paper proposes new physical explanations to explain altogether the impact of compressive strain, germanium content (in channel) and nitrogen content (in gate stack). Both compressive strain and Ge content impact on NBTI degradation is found to related to the modifications in the band structure in the channel. Excellent agreement between theory and experimental results shed new light on the NBTI degradation mechanism and the physics lying behind. Similarly, HCI degradation process dependences is well explained by the energy-driven model.

This work demonstrates that up to 74% energy efficiency can be gained by combining Body-Bias Process, Temperature and Aging compensation schemes altogether. This combination of compensation schemes offers the best energy efficiency gain as compared to recent results while guaranteeing high-level of robustness (<;1 ppm) and safety for automotive products.

This work explains how to run realistic electrical reliability qualification trials at system level. Experimental dataset is fully explained by new hierarchical modeling flow. This combined approach enables further tuning of the aging margin to adapt to system usage in the field. This work paves the way to Static Adaptive Voltage Scaling qualification at system level. This work also proposes a realistic solution for Dynamic Aging-aware Adaptive Voltage scaling based on pre-defined functions programmed in the SDK which improves the energy efficiency.

This paper shows new insights on the stochastic nature of aging-related timing impact in digital circuits. Varying critical paths through aging trigger the need for aging compensation control loop based on an unsupervised machine learning algorithm. Adaptive Resonance Theory (ART) algorithm is favored for its ability to handle the stability-plasticity dilemma.

In this work, we have demonstrated that many elements are needed on top of conventional foundry reliability knowledge to enable robust automotive products in compliance with all restrictive norms. For intrinsic reliability, both reliability models (a design compatible WLR description), and dynamic aging compensation schemes are required. For extrinsic failures, screening procedures require well documented usage and are shown in use for volume production to bring the failure rate level down below 1ppm automotive target. Altogether, the global approach developed in STMicroelectronics enable robust automotive products based on controlled and validated procedures.