This study examines different approaches to determining the chip failure rate that occurs due to dielectric cracking under C4 sites during chip joining. We show that testing of the strength of individual C4s by a single bump shear technique gives a strength distribution that is well described by a Weibull distribution with a Weibull modulus that lies in the range 10-20. Simulations of the spatial distribution of failing C4s during a chip joining test using this distribution, however, are found to be inconsistent with those observed experimentally. From this observation we conclude that the observed fails arise from a defect population that is not well characterized by single bump shear tests. We propose an alternative to SBS testing in which we directly count the number of fails that occur at a given stress level by comparing the location of the fails observed in multiple sonoscan images of chips to the C4 stress map calculated from a finite element model. An example is presented where the strength distribution of the defect tail is characterized from the analysis of C4 fails induced by an accelerated chip joining test. From this distribution we show how it is possible to project chip failure rates that arise from a manufacturing chip joining process.

The introduction of low-k & ultra-low-k dielectrics, lead-free (Pb-free) solder interconnects or C4's, and organic flip-chip laminates for integrated circuits have led to some major reliability challenges for the semiconductor industry. These include C4 electromigration (EM) and mechanical failures induced with-in the Si chip due to chip-package interactions (CPI). In 32nm technology, certain novel design changes were evaluated in the last Cu wiring level and the Far Back End of Line levels (FBEOL) to strategically re-distribute the current more uniformly through the Pb-free C4 bumps and therefore improve the C4 EM capabilities of the technology. FBEOL process integration changes, such as increasing the thickness of the hard dielectric (SiNx & SiOx) and reducing the final via diameter, were also evaluated for reducing the mechanical stresses in the weaker BEOL levels and mitigating potential risks for mechanical failures within the Si chip. The supporting white-bump, C4 EM and electrical/mechanical modeling data that demonstrates the benefits of the design and integration changes will be discussed in detail in the paper. Some of the key processing and integration challenges observed due to the design and process updates and the corresponding mitigation steps taken will also be discussed.

The paper examines the factors that affect the formation of delaminations under C4 joints during chip joining. Through multiscale finite element modeling and chip joining experiments we find that two important parameters determining the susceptibility to C4 delaminations( white bumps) are the effective modulus of the low-K levels in the BEOL stack and the thickness of the upper level in the stack that are built in an oxide dielectric. A simple effective spring model is developed to estimate the impact of metal loading at the via and line levels of interconnect structure on the effective modulus of the low-K dielectric stack. The importance of the effective modulus as a parameter controlling white bump formation is confirmed using a purpose built chip in which the effective modulus is modulated in each corner of the chip. Based on the observations from chip joining experiments it is demonstrated that failng BEOL structures can be differentiated from safe structures using a fail/safe map that is constructed using the effective modulus of the low-K levels and the thickness of the oxide levels as the two axes of the map.

Integrated circuits with Pb-free C4's have two major reliability concerns: thermal-mechanical stress induced mechanical fails within the Si chip and C4 electromigration (EM). Decreasing feature sizes, and increasing power and performance requirements have exacerbated these concerns and necessitated the development of innovative solutions to address the reliability issues and support the building of more robust and reliable packaged parts. Aluminum (Al) pads have been historically used in the Far Back End of Line (FBEOL) levels of the Si chip primarily for mechanical and Chip Package Interactions (CPI) benefits. Previous studies have shown that the Al pads used in legacy FBEOL process integration can serve as a stress redistribution layer to dissipate the detrimental thermal-mechanical stresses from reaching the underlying weaker BEOL ULK/Low-K levels. Aluminum processing in the wafer fab however typically uses carcinogenic chemicals such as hexavalent chromium for passivation and for corrosion inhibition. The current work evaluates non-Al FBEOL structures for the obvious environmental reasons but also as means for reducing processing costs and fab cycle times. Mechanical finite element analysis have been performed to determine the effect of the FBEOL structural changes on the stresses in the ULK/Low-k BEOL levels. White “C4” bump and C4 EM data comparing the Al pad structure to the non-Al pad structures will also be reviewed and some of the key process integration challenges with the non-Al structures will be discussed.

Chip-Package Interaction (CPI) related failure risk has increased in organic laminate-based electronic packages fueled in part by certain industry-segments' requirements for larger silicon die size and signal performance. CPI-related stresses increase directly with radial distance from the center of the die, known as distance from the neutral-point (DNP). The resulting risk of local delamination (White Bumps, WBs) in the silicon back-end-of-line (BEOL), fracture of C4 interconnections and failure of underfill and chip ultimately impact electronic package reliability. Named from the notable visible white halo or circle around a C4 in a CSAM (C-Mode Scanning Acoustic Microscopy) image, WBs are the prime indicator of a CPI-related failure event in an organic laminate-based electronic package. Laminate and BEOL design, specifically wiring proximal to the C4 interconnection, are known to influence WB reliability. In this paper we specifically study the effect of laminate and BEOL design on the generation of white bumps. Four different chip designs, some of which are more susceptible to WBs than others are mated with both product-design and "flat" laminates, or laminates consisting of only a core and single copper layer on each side. Our ultimate goal is to highlight the silicon & laminate designs' ability to modulate WB occurrences, to create design ground-rules thereby relaxing the cost and facilitating the development of package assembly solutions. A comprehensive experiment was carried out to achieve these goals. As companion test vehicles to product laminates, four different flat laminate (0-2-0) designs were fabricated with several different core materials to both segregate the effect of laminate wiring design and modulate the overall laminate coefficient of thermal expansion (CTE). Four separate chip designs were used to study the effect of the back end of line design. Thermal stress was induced in the experiment using a high-cooling rate or "hammer" chip-j- in (HCJ) reflow profile which drives a higher C4 shearing stress than with the nominal profile. The occurrence of WBs was then monitored while the test vehicles were repeatedly subjected to the hammer profile in a controlled hammer thermal cycling (HTC) process. Diagnostic measurements including 3D Surface Metrology and CSAM were performed after each HTC cycle to monitor both laminate warpage and WB occurrence respectively. White Bump evolution was statistically analyzed and correlated to each die design, laminate cross-sectional design and CTE. Results demonstrated the importance of laminate design in that the flat laminates consistently lead to fewer WBs than product laminates. Lower-CTE laminates also result in fewer WBs than product laminates.

One of the major reliability concerns of current and next generation integrated circuits is mechanical failure due to stresses induced by the chip-package interactions (CPI). The packaged parts are subjected to thermal-mechanical stresses due to a mismatch of the coefficient of thermal expansion of the Si, lead-free C4 bumps, and the organic flip-chip substrate leading to mechanical delamination or cracking in the weaker low-k/ultra-low K films within the chip. This work discusses the role of Aluminum (Al) pads in the far-back-end-of-line (FBEOL) levels of the chip in CPI stress mitigation of the weak low-k and ultra-low k (ULK) BEOL levels. The affect of the Al pad thickness, size and shape on the CPI stresses have been studied by means of 3D mechanical finite element analysis. “White C4” bump data showing the benefits of increasing the thickness of the Al pads and growing the Al pad size to be larger than the under bump metallurgy (UBM) diameter in alleviating detrimental stresses from the weak BEOL levels is also been discussed in the paper. This paper also outlines through mechanical modeling and “white C4” bump data the reduction in CPI stresses in the weaker BEOL levels with increasing thickness of the FBEOL hard dielectric.

Two key C4 reliability concerns for the current and next generation integrated circuits are electromigration (EM) and "white C4" bumps caused by the stresses induced by die-package interactions.This paper discusses novel design and integration changes in the final polymeric passivation via (FV) in order to mitigate white bump and chip-package interaction (CPI) stresses in the ultra-low k (ULK) BEOL levels and also meet lead-free C4 EM requirements.FV design changes such as strategically offsetting a single or multiple FV vias towards the center of the chip and thus to the compressive side of the C4 bump has been shown to reduce the stresses in the ULK levels due to chip package interactions and hence significantly reduce the number of white bump fails. Changing the shape of the FV via to strategically distribute current more uniformly through the C4 bumps has also been shown to improve the C4 EM performance significantly, while lowering the overall stresses in the chip. Effects of final passivation thickness and via diameter on the white bump stresses will also be discussed.Supporting white-bump, C4 EM and electrical/mechanical modeling data showing the benefits of the design and integration changes will also be discussed in detail in the paper.

The Cell Broadband Enginetrade (Cell BE) processor initially designed for high-end consumer electronics, has been enhanced by IBM for supercomputer applications. The enhancements to the chip also necessitated the design and development of a new package. The modifications to the chip included replacement of the 3.2 Gb/s XDR interface with a 800 Mb/s DDR2 interface of equal bandwidth. This required the addition of several hundred chip-level connections (C4's) and package BGA balls. Incorporating this and other enhancements to the chip resulted in a ~20% larger chip and a larger and more complex package. Additional noise from this large memory interface also drove decoupling requirements that necessitated mounting capacitors on both the top and bottom sides of the package. This paper describes the design of this new package as well as the analysis and characterization techniques used to address the packaging concerns outlined above. It includes a comprehensive noise analysis as well as a thorough characterization of the DDR2 interface in the final prototypes. The paper also outlines the design and analysis of the power distribution to the various voltage domains on the chip. Along with electrical design and performance, the paper also includes finite element modeling of the mechanical stresses resident in this FCPBGA package. Finally, the concluding portions of the paper will discuss the trade-offs between electrical performance and mechanical stability, reliability and relative cost.

Ultra low-k (ULK, k=2.4) dielectric has weaker mechanical properties than first generation low-k films (k=3.0). The introduction of ULK into advanced back end of lines (BEOL) presents a significant challenge due to chip package interaction (CPI) where the packaged die is cycled over a temperature range and the resulting stress can cause ULK BEOL delamination. To avoid CPI failure detailed modeling from the package down to the BEOL must be coupled with quantitative material property measurement. In this paper multi-level finite element models have been used to investigate the parameters which drive CPI failure. It is found that the defect size in the BEOL and the package geometry are key drivers for delamination. Finally, this paper presents a detailed example of the utility of modeling to optimize dicing to reduce defect size, and provide targets for crackstop toughness, which has resulted in a successful reliability qualification of the porous SiCOH (k=2.4) for 45 nm BEOL technology with an organic flip-chip package.

Technology migration of the Cell Broadband Enginetrade (BE) Microprocessor to 65 nm chip technology precipitated a redesign of the original IC packaging. While many of the design changes were necessitated by the chip technology migration, other modifications were implemented to enhance the robustness and overall manufacturability of the product. This paper will discuss key aspects of the 65nm chip technology that drove changes to the package design and also describe some of the modifications to enhance the manufacturability of the product. The paper will outline the statistical analysis, modeling, simulation and characterization employed in the electrical and thermal design, specification and tolerancing of the microprocessor package. The paper will be of specific interest to those involved in the cost-effective, high performance IC package design and development and will be of general interest to those developing and refining analysis methods employed in overall design and technology trade-offs in advanced packaging.

Low-k dielectric is used in advanced high performance CMOS chips to reduce wiring capacitance and power consumption. To get more benefit the dielectric constant has been constantly reduced, and currently is in the ultra low-range below 2.5. This is achieved by introducing porosity in low-k dielectric, which often compromises the mechanical properties such as the modulus and fracture toughness. For example, the cohesive strength of a porous dielectric is about a third of that of silicon dioxide. The weak mechanical properties pose challenges from ultra low-k/copper integration to chip packaging. When an ultra low-k/copper chip is packaged and tested in thermal cycling, dielectric can result in cracking and delamination due to the weak mechanical properties. To ensure packaged chip reliability the interaction of chip and package must be studied and understood.

We present a thermo-mechanical characterization of organic substrates that accounts for heterogeneity both in the in-plane and out-of-plane directions. Systematic observation of the board files of a number of substrates of commercial interest reveals primarily three recurrent topological arrangements of copper and polymer; for each arrangement, the in-plane effective thermo-elastic properties are calculated via appropriate composite materials models. The averaging process in the out-of-plane direction (i.e. the stacking effect) is performed using standard laminated plate theory. The model is successfully applied to various regions of three organic substrates of interest (mainly differing in core thickness): the analytically calculated effective Young’s moduli (E) and coefficients of thermal expansion (CTE) are shown to be typically within 10% of the experimental measurements. An important attribute of this model is its ability to provide substrate description at various levels of complexity: a few effective properties are outputted that can be useful for further purely analytical investigations; at the same time, the model provides the full stiffness matrix for each region of the substrate, to be used for more detailed finite elements simulations of higher-level structures (e.g. silicon die/underfill/substrate/cooling solution assemblies). Preliminary application of this model to the warp analysis of a flip-chip is presented in the end.

Integration and development of Cu Back-End of Line (BEOL) with PECVD low-k organosilicate glass (OSG, also called SiCOH, carbon-doped oxide, CDO, etc.) for 130 nm and 90 nm CMOS technologies has been reported by a number of institutions. Here we report on a Cu/SiCOH technology which has similarities, but also enhanced integration and reliability characteristics while preserving the R and C performance levels. These enhancements have led to excellent reliability results reported here, and are expected to increase the robustness to high-volume manufacturing and extendibility to next-generation smaller dimensions. The SiCOH and cap mechanical, chemical, and electrical strengths are increased, as well as associated interfacial adhesions. These combine with an optimized Cu metallization. As chip-package reliability is most at risk for low-k dielectrics, improvements have been brought into the BEOL level structure, the kerf design, and in some cases new packaging materials. When combined with the dielectric material and interface improvements, redundancy exists in the protection against potential chip-packaging failures. No failures occur in the full rounds of chip-package reliability stress testing done here on multiple wirebond and flip-chip packages. These packaging and other reliability results are presented, including BEOL-specific tests [electromigration (E-M), stress-migration (S-M), time-dependent dielectric breakdown (TDDB), thermal cycling (T/C)], environmental [temperature-humidity-bias (THB)], and functional stressing of product modules. The stress criteria and results exceeded JEDEC standards. All Cu/SiCOH tests passed at the same levels as our concurrent 90 nm Cu/SiOF technology.

A summary of chip-to-package interaction (CPI) evaluations for a 90 nm PECVD low k technology will be discussed. This review will cover a 90 nm technology that uses Cu dual damascene interconnections with a SiCOH (K /spl sim/ 3.0) CVD BEOL insulator stack across multiple wirebond package types and flipchip C4 ceramic and organic packages. It will be shown that with the use of IBM's internally engineered SiCOH BEOL insulator, CPI is not an issue with this technology node.

We report a comprehensive characterization of a 90 nm CMOS technology with Cu/SiCOH low-k interconnect BEOL. Significant material and integration engineering have led to the highest reliability, without degrading the performance expected from low-k. Results are presented on every aspect of BEOL and chip-package reliability, yields, low-k film parameters, BEOL capacitances and circuit delays on functional chips. All results meet or exceed our concurrent 90 nm Cu/FTEOS technology, and support extendibility to 65 nm.