When PCBs in electronics assemblies absorb moisture in humid environments, a swelling hygroscopic stress is developed in the PCB. The induced swelling stresses cause the PCB to deform and expand in volume, and may adversely affect the connected solder joints, and limit their lifetime. We developed a non-linear finite element analysis to investigate the effect of PCB moisture absorption and swelling on damage accumulation in BGA solder joints of a ceramic component. For this purpose, moisture diffusion in PCB was modelled by Fick’s law, which enables calculation of moisture concentration and the resulting deformation in PCB. The solder joints attaching the component to the PCB are affected by PCB deformation, and may develop inelastic stresses and strains. A viscoplastic material model was used to represent solder inelastic behaviour, and capture its damage evolution. The effect of PCB thickness on the solder maximum stress was also studied. The simulation results provide a framework to investigate the effect of humid environments on solder joints reliability.

Graphene layers have a very high basal plane thermal conductivity, but a low conductivity out -of-plane. When placed on a heat source, they can efficiently spread heat laterally, but not vertically. To fully exploit ultrahigh basal plane thermal conductivity of graphene layers, they can he assembled vertically. We examine the efficiency of vertically aligned graphene layers as thermal interface material (TIM) for gallium nitride (GaN) high electrons mobility transistors (HEMTs) with ceramic packages. The junction temperature (T-J) is directly measured using thermocouples bonded to the die. The measurements are done under free convection in the ambient. The graphene results are compared with two conventional TIMs. It is shown the graphene TIM can lower the Ti by at least 5 degrees C. More temperature reduction is expected when testing with forced cooling. A transient thermal finite clement model is also used for temperature prediction, showing good agreement with the experimental data.

The availability of data and AI-based methods have in recent years advanced the field of prognostics and health management. However, making accurate predictions of Remaining Useful Life (RUL) on products being used in operational environments, based on lifetime models from accelerated ageing experiments in the lab, is not straightforward. This paper introduces a recently patented method [1] for correlating lab-measured accumulated damage - gathered through accelerated aging experiments - with the RUL of products in the field, specifically with respect to the degradation mechanisms observed during testing. The method bridges the gap between prediction models developed from datasets recorded in a lab, to datasets available in the field. The method is based on the following steps: (i) mapping of the degradation process, (ii) exposure of samples to different levels of degradation, (iii) insertion of degraded samples in the final products, (iv) measurement of product-level responses to the different levels of degradation, and (v) comparison of those degradation responses to data from products in the field. One example of a degradation mechanism (wire bond lift-off) in power semiconductor packages is used to illustrate the method. However, the method is technology agnostic and can generally also be used for batteries, electric motors, or any application where a degradation can, with good accuracy, be modelled in the lab.

High-density electronics packaging requires fabrication of intricate conductive and dielectric features within a dense three-dimensional structure. Simultaneous deposition of both conductive and insulative printing materials using multimaterial additive manufacturing (AM) provides new opportunities to fabricate electronics packages with complex designs. This article reports the first demonstration of fully printed power die-embedded electronics package for wide band-gap devices. For this purpose, multimaterial inkjet AM was used to print a 0.5-mm thick electronics package for gallium nitride (GaN) power chips. The conductive parts of the package, including traces and vias, were printed using a high electrical conductivity silver ink, while a polyimide ink was used to print dielectric parts. The electrical characterization tests showed the reasonable performance of the printed package. While the conventional embedded packaging includes many steps such as laminating, plating, and drilling, which creates significant material waste and environmental issues, the proposed AM approach is done in a single step without material waste.

To generate data used for developing schemes and models for CM, PHM, and for estimating RUL of power electronic devices, accelerated aging experiments in the form of power cycling are often performed. In these experiments, a set current is passed through the power devices and is turned on and off in regular cycles. Due to the mismatch in CTEs of the materials in the devices, the on/off cycles will generate thermally induced stress in the various material interfaces, which is the main cause of failures. Most of the power cycling setups that are currently used can only manage a single set on-state current level and fixed on/off times (which is also the common standard for lifetime testing); a condition that is very far from most real applications. The experimental setup described here is based on a Gamry Reference 3000AEpotentiostat/galvanostat/ZRA working with a Gamry 30k Booster, which can be programmed to generate a variable load current profile and will thus enable the application of more realistic conditions for accelerated aging of power electronic devices in the lab. This will improve prognostics model development and provide excellent use cases for evaluating the capabilities of the prognostics algorithms for generalization to field conditions. The application of variable load profiles from the field, instead of the regular on/off cycles traditionally used, is not compatible with the commonly used method of using the chip itself as a temperature sensor. Instead, we here present a novel method of estimating the junction temperature using a device specific derivation of thermal parameters from the measured cooling block temperature, case temperature, and dissipated power in conjunction with simulations using the PySpice simulation package implemented in Python. The setup coupled with the new junction temperature estimation is an important step in enabling predictive maintenance of power devices that is currently missing from the power electronics community.

Remaining useful life prediction models are a central aspect of developing modern and capable prognostics and health management systems. Recently, such models are increasingly data-driven and based on various machine learning techniques, in particular deep neural networks. Such models are notoriously “data hungry”, i.e., to get adequate performance of such models, a substantial amount of diverse training data is needed. However, in several domains in which one would like to deploy data-driven remaining useful life models, there is a lack of data or data are distributed among several actors. Often these actors, for various reasons, cannot share data among themselves. In this paper a method for collaborative training of remaining useful life models based on federated learning is presented. In this setting, actors do not need to share locally held secret data, only model updates. Model updates are aggregated by a central server, and subsequently sent back to each of the clients, until convergence. There are numerous strategies for aggregating clients’ model updates and in this paper two strategies will be explored: 1) federated averaging and 2) federated learning with personalization layers. Federated averaging is the common baseline federated learning strategy where the clients’ models are averaged by the central server to update the global model. Federated averaging has been shown to have a limited ability to deal with non-identically and independently distributed data. To mitigate this problem, federated learning with personalization layers, a strategy similar to federated averaging but where each client is allowed to append custom layers to their local model, is explored. The two federated learning strategies will be evaluated on two datasets: 1) run-to-failure trajectories from power cycling of silicon-carbide metal-oxide semiconductor field-effect transistors, and 2) C-MAPSS, a well-known simulated dataset of turbofan jet engines. Two neural network model architectures commonly used in remaining useful life prediction, long short-term memory with multi-layer perceptron feature extractors, and convolutional gated recurrent unit, will be used for the evaluation. It is shown that similar or better performance is achieved when using federated learning compared to when the model is only trained on local data.

Residual stresses created during the packaging process can adversely affect the reliability of electronics components. We used incremental hole-drilling method, following the ASTM E 837-20 standard, to measure packaging induced residual stresses in discrete packages of power electronics components. For this purpose, we bonded a strain gauge on the surface of a Gallium Nitride (GaN) power component, drilled a hole through the thickness of the component in several incremental steps, recorded the relaxed strain data on the sample surface using the strain gauge, and finally calculated the residual stresses from the measured strain data. The recorded strains and the residual stresses are related by the compliance coefficients. For the hole drilling method in the isotropic materials, the compliance coefficients are calculated from the analytical solutions, and available in the ASTM standard. But for the orthotropic multilayered components typically found in microelectronics assemblies, numerical solutions are necessary. We developed a subroutine in ANSYS APDL to calculate the compliance coefficients of the hole drilling test in the molded and embedded power electronics components. This can extend the capability of the hole drilling method to determine residual stresses in more complex layered structures found in electronics.

Silicon carbide (SiC) power devices are steadily increasing their market share in various power electronics applications. However, they require low-inductive packaging in order to realize their full potential. In this research, low-inductive layouts for half-bridge power modules, using a direct bonded copper (DBC) substrate, that are suitable for SiC power devices, were designed and tested. To reduce the negative effects of the switching transients on the gate voltage, flexible printed circuit boards (PCBs) were used to interconnect the gate and source pins of the module with the corresponding pads of the power chips. In addition, conductive springs were used as low inductive, solder-free contacts for the module power terminals. The module casing and lid were produced using additive manufacturing, also known as 3D printing, to create a compact design. It is shown that the inductance of this module is significantly lower than the commercially available modules.

Compared with silicon-based power devices, wide bandgap (WBG) semiconductor devices operate at significantly higher power densities required in applications, such as electric vehicles and more electric airplanes. This necessitates the development of power electronics packages with enhanced thermal characteristics that fulfill the electrical insulation requirements. The present research investigates the feasibility of using ceramic additive manufacturing (AM), also known as three-dimensional (3-D) printing, to address thermal and electrical requirements in packaging gallium nitride (GaN)-based high-electron-mobility transistors (HEMTs). The goal is to exploit design freedom and manufacturing flexibility provided by ceramic AM to fabricate power device packages with a lower junction-to-ambient thermal resistance ( $R_{\theta \text {JA}}$ ). Ceramic AM also enables incorporation of intricate 3-D features into the package structure in order to control the isolation distance between the package source and drain contact pads. Moreover, AM allows to fabricate different parts of the packaging assembly as a single structure to avoid high thermal resistance interfaces. For example, the ceramic package and the ceramic heatsink can be printed as a single part without any bonding layer. Thermal simulations under different thermal loading and cooling conditions show the improvement of thermal performance of the package fabricated by ceramic AM. If assisted by an efficient cooling strategy, the proposed package has the potential to reduce $R_{\theta \text {JA}}$ by up to 48%. The results of the preliminary efforts to fabricate the ceramic package by AM are presented, and the challenges that have to be overcome for further development of this manufacturing method are recognized and discussed.

As the automotive industry shifts towards the electrification of drive trains, the efficiency of power electronics becomes more important. The use of silicon carbide (SiC) devices in power electronics has shown several benefits in efficiency, blocking voltage and high temperature operation. In addition, the ability of SiC to operate at higher frequencies due to lower switching losses can result in reduced weight and volume of the system, which also are important factors in vehicles. However, the reliability of packaged SiC devices is not yet fully assessed. Previous work has predicted that the different material properties of SiC compared to Si could have a large influence on the failure mechanisms and reliability. For example, the much higher elastic modulus of SiC compared to Si could increase strain on neighboring materials during power cycling. In this work, the failure mechanisms of packaged Si- and SiC-based power devices have been investigated following power cycling tests. The packaged devices were actively cycled in 4.5 s heating and 20 s cooling at ΔT = 60–80 K. A failure analysis using micro-focus X-ray and scanning acoustic microscopy (SAM) was carried out in order to determine the most important failure mechanisms. The results of the analysis indicate that the dominant failure mechanism is wire bond lift-off at the device chip for all of the SiC-based devices. Further analysis is required to determine the exact failure mechanisms of the analyzed Si-based devices. In addition, the SiC-based devices failed before the Si-based devices, which could be a result of the different properties of the SiC material.

The increasing complexity of electronics in systems used in safety critical applications, such as self-driving vehicles, requires new methods to assure the hardware reliability of the electronic assemblies. Prognostics and health management (PHM) that uses a combination of data-driven and physics-of-failure models is a promising approach to avoid unexpected failures in the field. However, to enable PHM based partly on physics-of-failure models, sensor data that measure the relevant environment loads to which the electronics are subjected during its mission life are required. In this work, the feasibility to manufacture and use integrated sensors in the inner layers of a printed circuit board (PCB) as mission load indicators measuring impacts and vibrations has been investigated. A four-layered PCB was designed in which piezoelectric sensors based on polyvinylidenefluoride-co-trifluoroethylene (PVDF-TrFE) were printed on one of the laminate layers before the lamination process. Manufacturing of the PCB was followed by the assembly of components consisting of ball grid arrays (BGAs) and quad flat no-leads (QFN) packages in a standard production reflow soldering process. Tests to ensure that the functionality of the sensor material was unaffected by the soldering process were performed. Results showed a yield of approximately 30% of the sensors after the reflow soldering process. The yield was also dependent on sensor placement and possibly shape. Optimization of the sensor design and placement is expected to bring the yield to 50% or better. The sensors responded as expected to impact tests. Delamination areas were present in the test PCBs, which requires further investigation. The delamination does not seem to be due to the presence of embedded sensors alone but rather the result of a combination of several factors. The conclusion of this work is that it is feasible to embed piezoelectric sensors in the layers of a PCB.

Lead-free tin-based solder joints often have a single-grained structure with random orientation and highly anisotropic properties. These alloys are typically stiffer than lead-based solders, hence transfer more stress to printed circuit boards (PCBs) during thermal cycling. This may lead to cracking of the PCB laminate close to the solder joints, which could increase the PCB flexibility, alleviate strain on the solder joints, and thereby enhance the solder fatigue life. If this happens during accelerated thermal cycling it may result in overestimating the lifetime of solder joints in field conditions. In this study, the grain structure of SAC305 solder joints connecting ceramic resistors to PCBs was studied using polarized light microscopy and was found to be mostly single-grained. After thermal cycling, cracks were observed in the PCB under the solder joints. These cracks were likely formed at the early stages of thermal cycling prior to damage initiation in the solder. A finite element model incorporating temperature-dependant anisotropic thermal and mechanical properties of single-grained solder joints is developed to study these observations in detail. The model is able to predict the location of damage initiation in the PCB and the solder joints of ceramic resistors with reasonable accuracy. It also shows that the PCB cracks of even very small lengths may significantly reduce accumulated creep strain and creep work in the solder joints. The proposed model is also able to evaluate the influence of solder anisotropy on damage evolution in the neighbouring (opposite) solder joints of a ceramic resistor.

The overall objective of the project wearITmed, Wearable sensors in smart textiles, is to develop a novel wearable sensor system demonstrator. This sensor system aims to monitor symptoms of neurological disorders such as epilepsy, Parkinson's disease and stroke. The wearable sensor system demonstrator, including both integrated gyros/accelerometers and textile sensors, is useful for the evaluation of clinically relevant movement patterns and other physiological parameters, and further to establish disease discriminating and treatment responsive objective variables. The work presented in this paper is focused on ensuring that the wearable sensor system can be cleaned and washed without first removing the electronics. The work includes three main areas; the adhesion and architecture, the molding and finally the washing test performance. Standard wettability and peel tests (Volvo Standard STD 185-0001) were performed on standard test board IPC-B-5 and IPC-9202 test vehicle for selecting the best adhesive and encapsulation materials in form of an epoxy (Epotek 302-3M) and a medical approved silicone (Nusil MED-6019). The molded components were washtested (Standard SS-EN ISO 6330:2012) followed by testing of the electrical resistance (Standard IPC-9202). As a result a total of 22 garments were produced with four individually mounted boards in each garment. The tests showed that the wearable sensors passed the washing tests and were still functional after 10 repeated washing cycles without any change or degradation in resistance or sign of electrical failure. The wearable electronics therefore meets the requirements of being simultaneously resistant to; water, temperature (40 °C), chemical detergents and dynamic forces.

Lead-free solder joints have been shown to increase the risk for crack formation in the PCB laminate under the solder pads. As such cracks propagate during thermal cycling, they decrease the strain imposed on the solder joint by acting as strain relief. In accelerated thermal cycling, these joints have been found to remain virtually undamaged even after a very high number of cycles. If these cracks do not form or propagate to the same extent under milder cycling conditions, typical of service conditions, it may lead to an overestimation of the fatigue life of the solder joints in accelerated testing. In this work, the extent of strain relief and the influence of grain orientations on the initiation and propagation of these cracks are investigated through FE-modelling and compared to what has been experimentally observed for cross-sections of solder joints moulded in epoxy resin with added fluorescent agent and inspected using UV-light and electron backscatter diffraction. Due to the strong anisotropy of lead-free solder joints, the stress transferred to the laminate will vary significantly depending on grain orientation. The presence of these laminate cracks adds another layer of uncertainty to the already complex SnAgCu system, where the strong effects of anisotropy, the continuously evolving secondary precipitate coarsening and its interaction with the recrystallisation process govern the damage evolution. If these effects are not properly accounted for, the interpretation of thermal cycling or modelling and simulation results may be strongly misleading.

The three year EU project SMARTER-SI that ends in January 2018 has tested a new concept for small lot manufacturing for SMEs which we call the Cooperative Foundry Model (CFM). During previous research, all RTOs have completed building blocks, i.e. components or parts of systems which are readily available and characterized by their high Technology Readiness Level (TRL). These building blocks are combined and integrated in so-called Application Experiments (AEs), thereby creating innovative Smart Systems that serve the SMEs' needs. Four pre defined AEs have been presented before [1] and in this paper, six additional AEs will be presented: i) a smart sensor for pneumatic combined clutch and brakes, ii) smart well plates for tissue engineering integrating continuous, non-invasive TEER iii) microclimate sensor for moisture applications, iv) LTCC-Si-Pressure Sensor, v) miniaturized capillary electrophoresis system for bio analysis, and vi) a MEMS sensor module for respiratory applications. Finally, a brief description of ongoing standardization efforts is presented.

The three year EU project SMARTER-SI that started in February 2015 has developed and tested a new production platform for smart systems that offer SMEs and “mid-cap” companies help to manufacture small and medium volumes. The ultimate goal of this project is to test a new concept for small lot production, which we call the Cooperative Foundry Model (CFM). The CFM is tested by combining components or parts of systems (building blocks) already developed by the RTOs involved in the project in so-called Application Experiments (AEs), thereby creating innovative Smart Systems which serve SMEs' product needs. During the first two years, four predefined AEs have been developed that consist of i) a multi-parametric point of care testing (POCT) device, ii) a dew-point measurement system, iii) a CO2 measurement system, and iv) a portable device that can be used to screen water quality.

The microstructure of lead-free solder joints often consists of only one or a few randomly oriented tin grains as a result of a large degree of undercooling during solidification. Due to the severe anisotropy of single crystal Sn and the random nature of the microstructure, the stress state and microstructural evolution of each joint will be unique. The orientation of the c-axis of the Sn crystal will strongly affect localized strain induced by temperature cycling, influencing the recrystallization process and thus the damage evolution in the solder joints. This will have strong implications on the reliability of lead-free solder joints and the accuracy of the predictions made with the current standard practices in virtual qualification. As a result of this random distribution of single-grained solder joints, joints to fail first in BGAs are not necessarily only dependent on the distance to neutral point, but rather the combination of location and microstructure of individual joints. In this work, the effect of location and orientation of single-grained solder joints in a CTBGA208 lead-free package were investigated through thermo-mechanical finite-element simulation and were supported by experimental findings of the same package through failure analysis and microstructural investigations using electron backscatter diffraction (EBSD) as well as polarized light microscopy. Due to the lack of data on the material properties of single-grained Sn-based, Pb-free solder joints, the anisotropic elasticity of pure Sn has been combined with the isotropic viscoplastic constitutive models commonly used in the literature.

COSIVU is a three year collaborative research project that ended in September 2015 and which has been funded within the European Green Car Initiative (now the European Green Vehicle Initiative). COSIVU addresses one of the most critical technical parts in fully electrical vehicles (FEV) besides the energy storage system: the mechatronic drive-train unit. The COSIVU project has delivered a new system architecture for multiple wheel drive-trains by a smart, compact and durable single-wheel drive unit with integrated electric motor, full silicon carbide (SiC) power electronics (switches and diodes), a novel control and health monitoring module with wireless communication, and an advanced ultra-compact cooling solution. DfR utilizing FEM simulations ensures first time right solutions. This paper presents the main results including the architecture of the drive train solution as well as the modular design of the inverter based on Inverter Building Blocks, one per phase. Performance tests are presented here for the first time for both the heavy duty commercial vehicle solution performed in a test rig by Volvo, and the tests of the COSIVU solution adapted to a passenger car done by Elaphe.

Cooling power modules on both sides of the active switching devices reduces the operational junction temperature compared to conventional single sided cooling. In this work, thermal simulations of power modules based on single sided cooling concepts are compared with double sided cooling counterparts. Expected junction temperatures, maximum temperatures and maximum current capability is analyzed. In addition, experimental verification in the form of comparisons with thermal characterization tests for both single-and double sided power modules based on SiC bipolar junction transistors is presented. Results from simulations show that cooling of both sides of the active switching devices can reduce the thermal resistance by more than 40 percent. This number depends on the heat transfer coefficient. From one example, simulating a worst case stall condition of the electric machine, the use of double sided cooling reduces the maximum junction temperature from 167 °C to 106 °C at a load current of 300 A using a heat transfer coefficient of 4 kW/m2K and 4 kHz switching frequency. Furthermore, the temperature decreases to 97 °C if AlN-based DBC substrates are used instead of alumina DBCs. Results from the experimental comparison between double-and single sided cooling showed that the maximum temperature for a load current range of 15 A to 50 A was reduced by 18 percent to 55 percent by using double sided cooling. At a device temperature of 60 °C, the increased thermal capability of the double sided version allowed for a 20 A higher load current, which corresponded to operation under 50 percent higher power losses. Double sided cooling also increased the maximum current capability through a single SiC BJT by more than 20 percent beyond the maximum current capability through the single sided cooling version.