High-density fan-out interposer is a promising 2.5D package option based on redistribution layer (RDL) first technology. Test vehicles (TVs) were designed to validate manufacturing process capability, reliability, design rules, and electrical performance. The interposer used various trace widths (from 1.5 mu m to 4 mu m) and lengths (3 mm to 7 mm for high bandwidth memory (HBM) and 2 mm to 5 mm for die to die) serpentine and comb structures to detect manufacturing defects and reliability risks. Daisy chains were distributed at high-risk regions. Most recent build showed that 1 mu m/1 mu m trace width and spacing (L/S) can be achieved with optimized process and material. Differential phase length electrical coupons were designed inside one test vehicle for electrical characterization. The test chips were bonded to the high-density fan-out interposer with 25 mu m mu Bump. Underfill was applied, and the interposer wafer was molded and ground to target thickness. Singulated units were probed before stress tests. During fabrication, metal to dielectric material delamination was noticed where large metal planes exist. While low metal density would impact cleaning and plating, balanced and reasonable metal density was found to be critical for high-quality manufacturing process. During stress test, no broken trace was found, but short circuit was identified when higher voltage (>=1.8 V) was applied at biased highly accelerated stress test. Electrical tests were conducted from 1 GHz to 30 GHz. Cross section of real vehicle indicated that the actual dimension is close to design value. This study validates high-density RDL for 2.5D package through specially designed test vehicles.
The rapid increase in computational requirements of modern computing systems has led to exponentially increasing thermal design powers from the processors. Traditional air-cooling methods have reached their limits, being unable to handle the component level heat fluxes and rack level power densities of next generation data centers. A transition to single-phase immersion cooling is an effective strategy to properly manage the heat fluxes from the next generation processors, all while offering improved energy efficiency, decreased water usage, and less data center whitespace. To fully embrace the benefits of immersion cooling, the heatsinks used on the processors must be well designed and optimized, necessitating rapid and robust performance models. This study presents the use of neural networks to develop models that predict performance characteristics of heatsinks in single-phase immersion cooling. The networks are trained on a synthetic dataset of 15,552 points, taking inputs of immersion fluid, flow conditions, and heatsink geometry. An analysis of the various architectural and training conditions is conducted, yielding networks with enhanced validation set accuracy. When inferenced in generalization, the networks exhibit accurate predictive capabilities (4.084% mean absolute percentage error) with an average inference time of 3.685 mu s. The networks are deployed in multivariable, multi-objective optimizations, completing various 10,000-point optimization analyses in under 3 s (average 2.21 s), with only a 3.9% difference from computational fluid dynamics optimization. A time-saving analysis is performed demonstrating the extreme order of magnitude reductions in design turnaround time possible.
The rapid advancement of electronic devices toward miniaturization, ultrathin designs, lightweight construction, and wearable functionality has made conventional rigid encapsulation technologies inadequate. As a result, flexible electronic encapsulation has emerged as a crucial solution, integrating flexible electronics with compliant materials to ensure reliable operation under mechanical deformations such as bending and folding. However, significant challenges remain, particularly in optimizing material performance, simplifying processes, and ensuring long-term reliability-especially in balancing mechanical flexibility with electrical conductivity and overcoming the limitations of traditional fabrication methods. This review provides a comprehensive summary of recent progress in flexible encapsulation technologies, focusing on key advances in materials, processing techniques, and application domains. Finally, we discuss future trends toward intelligent, miniaturized, and highly reliable systems, offering valuable insights for the next generation of flexible electronics.
Wafer warpage is a critical challenge in semiconductor fabrication that adversely affects manufacturing yield and device reliability. This challenge is intensifying due to increased device integration and significant thermal mismatches among deposited films. This study presents an approach that integrates finite element method (FEM) simulations with topology optimization (TO) to mitigate wafer warpage by optimizing the backside film. This method generates counteracting stresses designed to offset the original warpage. First, FEM simulations accurately captured the thermally induced warpage of a bilayer reference wafer to establish a baseline profile. Then, TO identified the optimal backside film configuration to minimize this warpage. Compared to conventional full-film attachment, the proposed method significantly reduces warpage while using less backside film material. The approach was validated across "smile," "cry," and "saddle"-type warpage scenarios, demonstrating that simulation-driven TO is an effective strategy for enhancing integrated circuit reliability and manufacturing productivity.
