RISC-V is a free and open-standard ISA based on RISC principles, allowing anyone to design, manufacture, and sell RISC-V chips and software. Its flexibility and growing ecosystem have made it popular in research, education, and industry, increasing the need for educational materials. This paper provides an in-depth description of the RVfpga course, which offers a solid introduction to computer architecture using the RISC-V instruction set and FPGA technology. It focuses on providing hands-on experience with real-world RISC-V cores, the VeeR EH1 and EL2 cores, developed by Western Digital and hosted by ChipsAlliance. The course targets students and educators in computing-related fields, enabling them to integrate practical RISC-V knowledge into their curricula. The course materials, which include detailed labs, setup guides, and the full SoC source code in System Verilog, are available for free. Students learn to compile, debug, and run C and assembly programs, to interact with built-in peripherals, to extend the SoC, and to explore microarchitectural features.

A highly efficient fetch unit is essential not only to obtain good performance but also to achieve energy efficiency. However, existing commercial fetch designs are not adaptable and depending on the program behaviour, they can be either insufficient or an overkill. A phase-based adaptive fetch mechanism that can be dynamically adjusted based on feedback information of the program behaviour is introduced. This design adds very little hardware complexity and relegates complex tasks to the software components. It is also very effective: saving 35% and 52% fetch energy on an average compared with a conventional and a trace cache-based fetch unit, respectively. At the same time, performance is improved by 4.7% and 0.8%, respectively.

Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with off-chip memory accesses. One of the main challenges of buffering a large number of instructions, however, is the implementation of a scalable and efficient mechanism to detect memory access order violations as a result of out-of-order scheduling of load and store instructions. Traditional CAM-based associative queues can be very slow and energy consuming. In this paper, instead of using the traditional age-based load queue to record load addresses, we explicitly record age information in address-indexed hash tables to achieve the same functionality of detecting premature loads. This alternative design eliminates associative searches and significantly reduces the energy consumption of the load queue. With simple techniques to reduce the number of false positives, performance degradation is kept at a minimum.

High-end processors typically incorporate complex branch predictors consisting of many large structures that together consume a notable fraction of total chip power (more than 10% in some cases). Depending on the applications, some of these resources may remain underused for long periods of time. We propose a methodology to reduce the energy consumption of the branch predictor by characterizing prediction demand using profiling and dynamically adjusting predictor resources accordingly. Specifically, we disable components of the hybrid direction predictor and resize the branch target buffer. Detailed simulations show that this approach reduces the energy consumption in the branch predictor by an average of 72% and up to 89% with virtually no impact on prediction accuracy and performance.

High-end processors typically incorporate complex branch predictors consisting of many large structures that together consume a notable fraction of total chip power (more than 10% in some cases). Depending on the applications, some of these resources may remain underused for long periods of time. We propose a methodology to reduce the energy consumption of the branch predictor by characterizing prediction demand using profiling and dynamically adjusting predictor resources accordingly. Specifically, we disable components of the hybrid direction predictor and resize the branch target buffer. Detailed simulations show that this approach reduces the energy consumption in the branch predictor by an average of 72% and up to 89% with virtually no impact on prediction accuracy and performance.