This paper presents a reconfigurable and energy-efficient digital spectrum shaping signaling (DSSS) for multidrop interfaces, where the output spectrum of the transmitted data is shaped using the 2-times repetitive block transmission to avoid frequency notches in the multidrop channel, thereby achieving a data rate up to 4x the first channel notch frequency. In conventional wireline transceivers (TRX), compensating for frequency notches requires a large number of decision feedback equalizer (DFE) taps at the receiver, resulting in significant area and power overhead. In contrast, the proposed DSSS architecture supports spectrum-efficient reconfigurable dual-mode NRZ/PAM4, reducing required equalization efforts and improving energy efficiency. The proposed scheme and its transmitter (TX) were first validated through event-driven behavioral simulations using XMODEL and verified with equipment-based measurements. Post-layout simulation results in 28nm CMOS process demonstrated 4 Gb/s data rate communicating over a channel having its first > 30 dB notch at 1 GHz, with a 235mV vertical eye opening and a TX energy efficiency of 0.39 pJ/b at 0.8V supply.
Compute-in-Memory (CiM) is emerging as a promising paradigm to design energy-efficient hardware accelerators for AI, addressing the processor-memory data transfer bottleneck. The popularity of CiM can be attributed to their ability to perform massively parallel in-situ matrix vector multiplications (MVMs), the dominant computation in neural networks (NNs). However, NNs used in NLP applications such as Long-Short Term Memory (LSTM) and transformers also frequently perform other operations such as transcendental functions (tanh, sigmoid, and softmax). To that effect, we present MemRaptor, utilizing CiM with magnetoresistive random access memory (MRAM) technology, that can perform both MVM and transcendental functions in the same memory array. MemRaptor overlays a read only memory (ROM) on an MRAM array through hard-wiring the connection of bit-cell with an additional bitline (a bit-cell connected to either of the bitlines but not to both), incurring no array area overhead and a minimal peripheral area overhead. Note, the bitline connection of bit-cell stores the ROM value while the magnetic tunnel junction (MTJ) in the bit-cell stores the RAM data. Particularly, the magnetization state of the 1T-1MTJ bit-cell in the array stores the weight value (RAM data) of the neural network, and the bitline connection of the bit-cell stores the look-up table (ROM data) used for computing transcendental functions. We demonstrate the working of our proposed design through circuit-level simulations for a 64x64 array, using a compact model of CoFeB/MgO PMA MTJ with 120% tunnelling magnetoresistance, 5k Omega R-ON, in 65nm technology. Further, we showcase the advantage of MemRaptor over standard MVM-based CiM accelerator architecture, PUMA, through comprehensive system-level evaluations for LSTM, BERT, and GPT models. Our results show up to 30% and 5.3% improvements in terms of throughput and energy-efficiency, respectively, on an average across different workloads.
Recently, compute-in-memory (CIM) has become a promising architecture for data-intensive applications such as deep learning. However, analog or digital CIM (ACIM or DCIM) faces some design challenges. ACIMs inherently have non-idealities, which lead to significant accuracy degradation. In addition, a substantial amount of power is consumed by analog-to-digital converters (ADC). On the other hand, DCIMs show an exponential increase in power consumption and computing cycles as the operand bit-width increases, particularly due to an accumulation stage. In this paper, to overcome these challenges, we propose a hybrid DCIM-ACIM architecture that consists of a content addressable memory (CAM) as DCIM and a cluster-based multi-cycle ACIM, called CAM-CIM. As a weight mapping strategy, we present a subword split mapping that assigns some MSBs to DCIM for improved accuracy and the remaining LSBs to ACIM for reduced ADC resolution. The accuracy of using the proposed CAM-CIM array is evaluated on various deep learning benchmarks from CNNs to Swin-Tiny. A 65nm CAM-CIM macro with either 3-bit or 4-bit ADCs shows 10.3x and 5.4x improvement in energy efficiency, on average, compared to CAM- and CIM-only architectures, respectively. Compared to recent CIM architectures, CAM-CIM demonstrates 1.4x higher energy efficiency.
Macro placement in the floorplanning stage is crucial as it marks the beginning of the entire VLSI physical design flow. Despite its significant impact on the final design quality, identifying the optimal macro placement for sign-off power-performance-area (PPA) remains challenging and often relies on empirical methods. Although recent algorithms for automatic macro placement leverage the relationships among macros and standard cells, they failed to fully address timing-related objectives. In this paper, we propose a timing-driven macro placement framework that utilizes connectivity and clocked element (e.g., flip-flop) information among macros for clustering and integrates dedicated timing costs throughout the entire process. We first utilize the Louvain algorithm to iteratively conduct multi-level clustering on a directed graph derived from the design RTL, with edge weights assigned based on the ratio of the number of logic gates and clocked elements between macros. At each clustering level, we utilize simulated annealing (SA) to determine the clusters' shape and placement. After the last iteration, we conduct macro placement per cluster using SA with our timing-related cost function. Finally, we refine the macro placement result to escape from the bottom-left arrangement, again guided by the timing-related cost function. Experimental results demonstrate that our macro placement framework successfully improves timing metrics, WNS and TNS, by 16.87% and 18.49% over state-of-the-art open-source macro placement, and by 6.59% and 15.54% over a commercial macro placement engine, respectively.
Transformer-based large language models (LLMs) impose significant bandwidth and compute challenges when deployed on edge devices. SRAM-based compute-in-memory (CIM) accelerators offer a promising solution to reduce data movement but are still limited by model size. This work develops a ternary weight splitting (TWS) binarization to obtain Brain-Floating-Point-16xINT1 (BF16x1-b) and INT8xINT1 (8-bx1-b) based transformers that exhibit competitive accuracy while significantly reducing model size compared to full precision counterparts. Then, a fully digital SRAM-based CIM accelerator is designed incorporating a bit-parallel SRAM macro within a highly efficient group vector systolic architecture, which can store one column of BERT-Tiny model with stationary systolic data reuse. The design in a 28nm technology only requires 2KB SRAM with an area of 2mm(2). It achieves a throughput of 6.55TOPS and consumes a total power of 312.5mW and 221mW at 400MHz, resulting in a state-of-the-art area efficiency of 3.3TOPS/mm(2) and normalized energy efficiency of 20.98TOPS/W and 34.35TOPS/W for BF16x1-b and 8-bx1-b respectively on BERT-Tiny model, demonstrating a 10.25x improvement in area efficiency and a 2.23x improvement in energy efficiency compared to other state-of-the-art counterparts. Additionally, our proposed configuration compresses the model size by 32% with only a 0.5% accuracy loss on SST-2.
Vision Transformers (ViTs) have become the backbone of numerous cutting-edge vision applications. The attention modules within ViTs play a crucial role in modeling spatial relationships between pixels. Although these attention modules enhance the accuracy of ViT models, they also increase computational demands, limiting the deployment of ViTs in edge computing environments. To address this issue, prior research has focused on optimizing ViTs from both software and hardware perspectives. A notable software optimization technique is reducing the image patches involved in attention computations. Two common methods to achieve this are window attention and patch pruning. However, they introduce new challenges for existing hardware platforms regarding attention computation. Therefore, it is essential to develop new hardware modules to simultaneously support pruned attention computations and efficient window shifts. In this study, we introduce an FPGA-based token reduction vision transformer accelerator called TRFPA. Experiments conducted on the Xilinx ZCU104 and Alveo U50 demonstrate that TRFPA outperforms previous FPGA-based ViT accelerators, achieving a 7x speedup and a 3x improvement in energy efficiency.
Transformer models have shown remarkable performance in AI tasks. However, their large model sizes and large-scale matrix computations heavily press the memory bandwidth. Compute-in-memory (CIM) solutions have emerged to address these issues by integrating computation into memory. Nevertheless, existing scalable and heterogeneous CIM designs further suffer from inefficiencies caused by isolated mapping strategies and communication redundancy. To address these issues, we propose Cross-Type Mapped Dataflow, an architecture-dataflow co-design that enables efficient and collaborative analog-digital CIM execution. Our approach features a heterogeneous analog-digital CIM architecture with flat network-on-chip (NoC) interconnects, enabling seamless cross-type communication. The core innovations include: a Hybrid Dataflow that schedules idle CIMs for cross-type collaboration on vector-matrix multiplication, and an In-Network Reduction (INR) mechanism that eliminates redundant data transfers by embedding Reduction operations within NoC communication. Experimental results show an average 3.57x speedup and 2.78x energy efficiency improvement over Homogeneous DCIM architecture. Optimized by the proposed Hybrid Dataflow and INR, our heterogeneous CIMs further achieve an average 4.63x speedup and 2.59x energy efficiency improvement over state-of-the-art X-Former-like design across various ViT workloads.
Fully Homomorphic Encryption (FHE) allows computations over encrypted data without sacrificing confidentiality, but its practicality is hindered by high computational demands and memory access constraints. While existing FHE accelerators focus on improving computational efficiency, they are often limited by the insufficient memory bandwidth and inefficient data transfer schemes, leading to significant bottlenecks, especially for processing large amounts of data. In this work, we evaluate whether OptoLink, a photonic interconnect architecture, is scalable and capable of providing high bandwidth to overcome these limitations. Leveraging Wavelength Division Multiplexing (WDM) with Space Division Multiplexing (SDM), OptoLink achieves an impressive bandwidth of 1.6 TB/s over 128 channels—a 300x improvement over traditional electronic network. Additionally, its ability to efficiently broadcast data and support parallel processing further enhances performance. The broadcasting capability not only enables parallelism but also reduces power consumption in earlier NTT stages, improving overall energy efficiency. With its improved data throughput, scalability, and lower latency, OptoLink offers a robust solution capable of satisfying the high data transfer and memory demands of current FHE accelerators.
Efficient polynomial multiplication in finite fields is vital for the design of high-performance on-chip cryptosystems. This need becomes even more significant in modern digital security systems that demand enhanced security strength and computational efficiency. Elliptic Curve Cryptography (ECC) is a public-key cryptography method that effectively balances security and performance using shorter key lengths. Recent developments in polynomial multipliers utilize various strategies, such as recursively splitting operand bits and using a blend of Karatsuba and overlap-free multipliers to recombine partial products. This mixed approach has demonstrated hardware and performance advantages over state-of-the-art techniques. Heuristically optimizing polynomial multipliers for ECC involves a design-space search using meta-heuristics to find optimal recursive configurations based on hardware parameters. The ECC processor is specifically engineered to incorporate these optimized polynomial multipliers. The design is implemented on a ZYNQ ZU-19EG FPGA board and synthesized using the Cadence Genus tool with a 45 nm technology node. This approach results in a 52.45% reduction in footprint, a 52.50% decrease in critical path delay, and a 73.19% improvement in the area-delay product. These improvements lead to a more hardware-efficient design, contributing to tighter and more secure cryptographic systems. The designs are freely shared with the research community for further use.
Due to its high speed and simple structure, the ChaCha20 algorithm offers an alternative to AES, making it well-suited for lightweight encryption in IoT devices [1]. However, its execution on traditional Von Neumann architectures incurs significant energy overhead due to frequent memory accesses. In-memory compute (IMC) architectures address this challenge by allowing computation directly within memory. Although these architectures are characterized by straightforward power performance and area parameters, designers leave out other critical design considerations that impact sustainability. As technology continues to evolve rapidly, it becomes increasingly important to assess the environmental impact of large-scale design architectures. In this paper, we present a secure and sustainable implementation of the ChaCha20 encryption algorithm using IMC architectures. We evaluated the trade-offs of implementing ChaCha20 in 6T, 9T, and 10T SRAM bitcell architectures by introducing a sustainability-focused metric alongside conventional parameters. The developed sustainability metric evaluates architectures based on the combined impact of the embodied and operational carbon footprint. Additionally, we assess the security of these architectures against power-based side-channel attacks using Welch’s t-test. Among the evaluated designs, the 6T implementation achieves the smallest area footprint but at the cost of degraded performance. In contrast, the 9T implementation preserves the performance of the 10T design while reducing area overhead. Furthermore, sustainability analysis based on the introduced metric identifies the 6T bitcell as the most sustainable option.
Computing technologies based on superconducting Josephson junctions, such as single-flux-quantum (SFQ) and half-flux-quantum (HFQ) circuits, are promising as next-generation computing platforms for their exceptional speed and low power consumption. Stochastic computing (SC), a non-deterministic computation approach known for its superior area efficiency, has attracted interest due to its compatibility with SFQ logic and its potential applications in hardware for machine learning. Existing multiplexer (MUX)-based SC adders using SFQ technology encounter challenges with accuracy, area efficiency, and power consumption. In this paper, we propose a low-power, compact, and correlation-insensitive SC adder that leverages the unique characteristics of the confluence buffer, a fundamental circuit element in SFQ and HFQ technologies. By adopting local two-phase clocking, our SC adders avoid computation inaccuracy due to correlation of input bit streams. Our evaluation results show that, compared with existing SFQ MUX-based SC adders, the proposed SFQ-based design achieves approximately 50% reductions in the number of Josephson junctions, implementation area, and power consumption. Furthermore, the proposed HFQ-based design reduces power consumption to approximately 1/3rd to 1/5th of SFQ-based designs for the same manufacturing technology.
Accurate power estimation early in the design cycle is crucial for the design of power-efficient System-on-Chips (SoCs). Power estimation has been researched at various levels of abstraction, with a well-known trade-off between efficiency and accuracy. Recent work has shown great promise for machine learning (ML) techniques to advance the state-of-the-art in power estimation. We propose ML-Power, the first ML-based framework that can address both key bottlenecks involved in power estimation, viz. simulation and power model evaluation. ML-Power builds and uses models that estimate power in each SoC block using a very small subset of internal signals, known as power proxies. ML-Power consists of two key components, PACE and SCOPE. PACE trains a sequence-to-sequence ML model to translate a transaction-level execution trace into a cycle-level trace of the power proxy signals, allowing much faster simulation models to be used in place of RTL simulation. SCOPE selects power proxies and trains ML-based power models for blocks (IPs) within the SoC. SCOPE improves upon prior work in ML-based power modeling by exploiting spatio-temporal correlations among SoC blocks to minimize the number of power proxies while also improving estimation accuracy. We evaluate ML-Power for an ARM SSE-300 SoC and two RISC-V based SoCs. Compared to prior state-of-the-art ML-based power estimation frameworks, SCOPE trains power models similar to 65x faster, picks 40% fewer proxies, and achieves 2% lower estimation error. ML-Power also achieves similar to 300x speedup over a commercial RTL power estimation tool with less than 7% error in per-cycle power estimates.
Security and privacy are key enablers (and often also a legal requirement) for a number of applications, including smart grid and smart cities, health care, data analytics, and personalized services. Because of this, research in the domain of security and privacy-preserving techniques is progressing at high pace. However, if on the one side the research community devoted large attention to the study of more efficient algorithms and the design of more efficient architectures implementing them, on the other, the energy cost and the energy implications of the use of these technologies have not yet been explored in the needed depth, with the majority of literature focusing on block ciphers. This tutorial exposes the community to the main current research results and best practices in this research area, and aims to foster the exchange of ideas between all the involved stakeholders. The tutorial presents the background and latest achievements in the field of energy assessment and reduction for security and privacy-preserving primitives. This tutorial covers the needed background on security algorithms, discusses their energy consumption, and presents, by means of relevant examples, how to design and implement security primitives that achieve a limited energy footprint. In particular, the focus is on two families of security primitives: block ciphers and privacy-preserving primitives. The tutorial introduces the basic concepts and the main algorithms belonging to these families, discusses recent advances in the domain, and presents in detail the energy consumption of these technologies and in their applications such as machine learning. Further, the tutorial will show optimizations that have been proposed to minimize the energy footprint of security primitives, with a particular focus on block ciphers, discussing also the design of lightweight and low-energy cryptographic algorithms. The tutorial concludes discussing open problems, limitations, and possible research directions. The tutorial is divided into three sections and will begin with a talk providing a detailed introduction of the needed concepts, to allow attendees not familiar with the topic to be able to successfully follow the whole tutorial. More in details, the sections are: • "Introduction to Security Primitives and Privacy Preserving Technologies". This talk will introduce the audience to the security primitives and the relevant privacy preserving technologies and protocols, [1] that will be analyzed in the rest of the tutorial. • "Energy Assessment of Security Primitives". This talk summarizes current research in energy assessment [2] of security primitives, reporting the method used to assess them and presenting literature result on the energy consumption of security primitives. The talk will conclude presenting open problems and future research directions. • "Energy Efficient Design and Implementation of Security Primitives". This talk reviews the strategies that have been applied to security primitives to reduce their energy consumption and presents the algorithms that have been designed, since the beginning, to achieve a limited energy footprint [3] , [4] . The talk will conclude presenting open problems and future research directions.
As the parameter size of deep neural networks (DNNs) increases, high bandwidth memory (HBM) is widely adopted to satisfy the growing demand for memory bandwidth. However, due to the shorter retention time caused by higher on-chip temperature, HBM requires more frequent refresh operations, resulting in significant refresh energy and performance overhead. In this paper, we propose SHIFT ECC, a lightweight and robust ECC scheme for INT8 quantized DNNs on HBM, to reduce refresh operations while maintaining inference accuracy. SHIFT ECC enhances DNN reliability by converting negative weights into positive weights, eventually mitigating the primary cause of retention errors (mostly 1.0 bit errors). Additionally, SHIFT ECC applies stronger ECC to the upper bits (more important bits) of DNN weights while protecting the lower bits (less important bits) with weaker ECC, which further enhances the robustness of DNNs with the same number of parity bits. Our evaluation results show that when the proportion of 1.0 bit errors is 100% and 99%, SHIFT ECC reduces average refresh energy by 32.6% and 35.0%, respectively, reducing average memory read latency by 21.7% compared to the state-of-the-art refresh reduction technique.
Quantization is a widely adopted method of reducing resource consumption of neural network models while maintaining good model accuracy. Ternary and Binary Neural Networks (TNNs and BNNs) can be implemented by lightweight bitwise operations and are thus very suitable for edge platforms. Existing efforts mainly optimize the bitwise computation algorithms for BNN inference. However, TNNs and mixed-precision Ternary-Binary Neural Networks (TBNs and BTNs) still lack optimized computing libraries on AVX2 and ARM CPUs. Their data preparation walks through the data multiple times, resulting in low data locality. Moreover, the popcount accounts for up to 28% of total operations in bitwise matrix multiplication, but the popcount has throughput of only 1 and no SIMD instructions in AVX2, becoming the central performance bottleneck. In this paper, we propose a faster inference method for TNNs, TBNs, and BTNs on AVX2 and ARM CPUs. First, we optimize the data preparation stage by fusing the quantization, bit-packing, and image-to-row into one loop to improve the data locality. Second, we propose an efficient bitwise matrix multiplication algorithm for AVX2 by replacing the low-throughput popcount instructions with high-throughput SIMD instructions and applying new data encoding. This algorithm reduces the total instruction count by 15% and brings 2.2x theoretical speedup. Third, we implement a fast C++ inference library for TNNs, TBNs, and BTNs with standard optimizations like blocking and loop unrolling. Benchmarking results show that our new matrix multiplication algorithm is up to 2.1x faster than the related work TAB on AVX2 CPUs. We further achieve layer-level speedup of up to 2.7x on AVX2 and 2.3x on ARM over the baseline for TNNs, TBNs, and BTNs. Moreover, we achieve 1.3-1.9x end-to-end speedup and 1.2-1.8x energy efficiency compared to TAB on Resnet, Darknet, and VGG models.
We recently proposed Radar-PIM, a Processing-in-Memory (PIM) solution for real-time, low-power UWB radar respiration detection. To meet stringent energy constraints for UAV-based rescue operations, we further developed Radar-PIM-Lite, significantly reducing resource usage and power consumption. We implemented a processor based on our proposed technology and validated its superior ultra-low-power performance and reliable real-time detection capability through FPGA prototyping and application demonstrations. We will showcase this FPGA-based Radar-PIM-Lite prototype through a live demonstration at ISLPED 2025.
We present a low-power, stochastic computing-based method for real-time video edge detection. Traditional Sobel-based pipelines are often resource-intensive and consume substantial power. In this work, we simplify the Sobel operator within a stochastic computing framework to achieve significant reductions in hardware complexity and energy consumption. We implement the proposed design on a Basys 3 FPGA interfaced with an OV7670 camera, demonstrating real-time performance. Experimental results show up to 17% energy savings, 84% reduction in LUT utilization, and a 68% decrease in RAM storage and a substantial reduction in hardware footprint compared to a traditional implementation. Demo video link: https://github.com/arghadippurdue/StoBelDemo.
This paper presents a single-ended four-level pulse-amplitude modulation (PAM-4) transceiver for next-generation high bandwidth memory (HBM) interfaces. Since HBM interfaces have over 1024 DQs, the interfaces need to improve energy efficiency and minimize area. The proposed PAM-4 transmitter employs capacitive drivers to extend bandwidth with low power and uses accumulation-mode NFET capacitors as AC coupling capacitors to reduce area. A high-level boosting technique (HLB) is introduced to compensate for the capacitance variation according to output voltage levels, thereby improving the ratio of level mismatch (RLM). A feed-forward equalization (FFE)-combined capacitive PAM-4 driver effectively removes inter-symbol interference (ISI), leading to higher data rates. To define the DC level without using dissipated static power, a ground-forcing technique is applied. The silicon interposer channel was emulated using a 5.9 mm on-chip wire. A prototype chip was fabricated in a 28 nm CMOS process and occupied 0.0039 mm2. The prototype achieves data rates of 16 Gb/s with an energy efficiency of 67.2 fJ/b/mm and RLM of 0.992.
The effective utilization of graph structures relies on obtaining high-quality graph embeddings. Traditional embedding algorithms, such as DeepWalk and Node2Vec, which rely on random walk sampling, encounter significant challenges when applied to large-scale graphs due to the substantial data transfer demands between storage and memory. To address these limitations, we propose AridWalk, which enables a Computational Storage Device (CSD) to perform random walks directly at the storage level, minimizing external data transfers by only transferring essential data. To address the constraints of limited computational resources in the CSD, AridWalk is designed to maximize DRAM utilization while significantly reducing internal data movements, specifically between internal DRAM and flash memory. Experimental results demonstrate that AridWalk substantially decreases internal data movement, providing an efficient and scalable solution for conducting in-storage random walks on large graphs.
Neuromorphic computing is emerging as a paradigm for high-performance, energy-efficient edge intelligence. Yet the transition from laboratory prototypes to deployable edge platforms is slowed by four intertwined obstacles: (1) complex near-sensor integration, where spiking inference must co-locate with analogue sensing to minimise latency and data-movement energy; (2) novel event-based optimisation, requiring weight compression and sparsity techniques tailored to event-driven workloads; (3) heterogeneous integration of emerging devices, such as RRAM and other non-volatile memories, into reliable, manufacturable stacks; and (4) novel security risks, including spike-pattern side channels and model-specific attacks that demand to develop neuromorphic security primitives. This paper surveys the state of the art across these four fronts, drawing on recent advances in spiking microcontrollers, mixed-precision compute-in-memory fabrics, sparsity-aware compilation, and hardware-anchored security primitives (physical unclonable functions, true random number generators, computing-in-memory-based cryptography). By distilling lessons from academic research and industrial prototyping, the paper outlines current solutions and future research directions aimed at accelerating the adoption of neuromorphic platforms in real-world edge AI systems.
