A fully integrated, non-frequency-translating, low-impedance transceiver (TRX) front end for cellular base stations (BSs) covering 1.25-5.5 GHz is presented. The transmitter (TX) features two variable gain feedback pre-power amplifier (PPA) stages, a power amplifier (PA), and an RF notch filter based on frequency translation for suppressing spurious signals. The receiver (RX) features a low noise amplifier (LNA), a variable gain amplifier (VGA), and an equalizer supporting three concurrent frequency bands with orthogonal frequency and gain tuning. The PA and LNA use a 12.5-Omega differential impedance, primarily to boost PA output power and bandwidth (BW). Special emphasis is put on the thermal analysis of the PA and the techniques to improve the cooling. When operating with full PA supply (7.4 V), including antenna-switch and package losses, the TX reaches a record saturated output power (P-sat) of 38.1 dBm at 3.4 GHz, and for a 100-MHz 16-QAM orthogonal frequency-division multiplexing (OFDM) signal at 2.7 GHz, the TX delivers an output power of 32.6 dBm with an error vector magnitude (EVM) of -17.6 dB, with a complete TX efficiency of 13.5%. With a reduced PA supply of 3.8 V, an 8 x 100 MHz 256-QAM OFDM signal with 21.6 dBm was measured with EVM < -31.1 dB. The TX filter achieves about 40-dB notch depth at 1-6-GHz notch frequencies, and the 20-and 30-dB rejection BW can be controlled from 1 to 10 MHz and from 0.4 to 4 MHz, respectively. The front end has an RX noise figure (NF) of 1.3-2 dB, while the third-order intercept point (IIP3) is above -12.4 dBm, at maximum gain (29 dB) over the frequency range of 1.55-4.8 GHz. The passive equalizer improves the RX interference handling and is analyzed using closed-form expressions. The active part of the die, manufactured in 22-nm fully depleted silicon on insulator (FD-SOI) CMOS technology, occupies 6.6 mm(2).

This paper presents a fully integrated non-frequency-translating transmitter covering 1.25-5.5 GHz. It features a highly linear and controllable pre-power amplifier (PPA), a low impedance class AB PA, and a transmit/receive switch (TRX-switch). Including TRX-switch losses, the transmitter reaches a state-of-the-art saturated output power of 38.1 dBm with a 1 dB output compression point of 37.4 dBm. Stimulated with a 100 MHz 16-QAM OFDM RF-signal, without predistortion and operating with 7.4 V PA supply, the transmitter delivers a 2.7 GHz modulated signal with an output power of 32.6 dBm and an error vector magnitude (EVM) of -17.6dB, with a complete transmitter efficiency of 13.5%. Operating at a reduced PA supply (3.8V) it can deliver >20dBm output power with <-33 dB EVM. To handle the high power dissipation, special emphasis is put on cooling of the die. The active part of the die, manufactured in 22 nm FD-SOI CMOS, occupies 3 mm(2).

In this work a front-end for a direct RF-sampling receiver implemented in 22 nm FD-SOI CMOS technology is presented. To achieve high blocker tolerance and wide bandwidth, an LNA with a differential input impedance of 12.5 Omega is designed. An off-chip wideband transmission line transformer is used to transform the 100 Omega antenna impedance to 12.5 Omega. The frontend also features a VGA which can program the gain with low penalty in dynamic range. Furthermore, an equalizer supports three concurrent frequency bands with orthogonal frequency and gain tuning for each. The front-end consumes 172 mA from a 1.5 V supply and has an NF of 1.3 to 2 dB, while the IIP3 is -12 dBm at maximum gain and the frequency range is 1.55 to 4.8 GHz. The equalizer improves the IIP3 by up to 12 dB at the frequencies outside the supported bands where blockers are expected.

Carrier aggregation (CA) is introduced in 3GPP LTE Rel-10 [1] to meet the demand for further increased bitrates. While LTE Rel-10 supports simultaneous reception of two carriers either in contiguous intra-band or in inter-band CA configuration, the upcoming LTE Rel-11 will add support for non-contiguous (NC) carriers within bands. Supporting NC CA in handsets is a demanding challenge for several reasons. Foremost, the total bandwidth spanned by the carriers may be several times the bandwidth of the individual carriers, possibly spanning an entire band with interfering signals between desired carriers. Furthermore, the distance between TX and RX carriers will vary and worse, may be much smaller than the fixed duplex distance for LTE Rel-8 and W-CDMA single carrier operation [2-5].

This paper presents a complex IF mixer for a double conversion receiver architecture to be used for non-contiguous dual carrier reception as specified in upcoming releases of 3GPP standards. The complex IF mixer contains four harmonic rejection (HR) mixers, each of which is implemented with 64 passive unit cell mixers, clocked by a ring-oscillator based phase-locked loop and driven by sequencers that represent thermometer-coded oversampled sinusoidal LO waveforms. Each HR mixer is followed by a buffer and a signal distribution network to enable separation of the two carriers as well as IQ-imbalance correction. The complex IF mixer supports reception of two carriers with up to 65 MHz separation using 12 samples per IF LO period and a clock frequency of 390 MHz. The IF mixer is implemented in 65 nm CMOS, has an area of 0.74 mm(2), draws 26 mA, and has a harmonic conversion lower than -68 dBc per harmonic.

Fast parallel multipliers that contain logarithmic partial-product reduction trees pose a challenge to simulation-based high-accuracy timing verification, since the reduction tree has many reconvergent signal branches. However, such a multiplier architecture also offers a clue as how to attack the test-vector generation problem. The timing-critical paths are intimately associated with long carry propagation. We introduce a multiplier test-vector generation method that has the ability to exercise such long carry propagation paths. Through extensive circuit simulation and static timing analysis, we evaluate the quality of the test vectors that result from the new method. Especially for fast multipliers with a pronounced carry propagation, the timing-critical vectors manage to stimulate a path, which has a delay that comes close to the true worst case delay. We investigate the complexity and run-time for the test-vector generation, and derive timing-critical vectors up to a factor word length of 54 bits.

Gate leakage power dissipation is predicted to overtake subthreshold leakage power within the next few years thus adding further problems for designers trying to meet a strict power budget. In this paper, a power cut-off technique is proposed, which in sleep mode suppresses not only subthreshold leakage but also gate leakage. The proposed technique displays a combination of low total leakage power and short wake-up time.

Traditionally, RTL power estimation techniques characterize a component for a fixed environment (most importantly load capacitance, activity, and operating frequency). This article presents a solution to problems originating from the ineluctably changing operating conditions such as differing load capacitance due to different applications; different activity and operating frequency. These techniques can be used in design power reduction.

A 3.5GHz 8-phase all-digital clock generator is fabricated in 150nm CMOS to achieve scalable 1.7/spl times/ frequency-range and 9ps end-to-end time resolution measured at 1.6V and 110/spl deg/C. A closed-to-open loop control scheme enables 32mW open-loop power consumption, 300/spl mu/W at clock gate-off, zero-cycle response during clock re-enable, and <4% static phase error.

We present a mixed-mode delay-locked loop (DLL) architecture intended for multiple-phase clock generation. In contrast to analog DLLs, the proposed architecture allows for clock-gating; moreover circuit simulations indicate that its performance (in terms of maximum frequency, frequency range, and low-speed power dissipation) is superior to that of a previously-reported, purely digital DLL.

We consider the power-optimal design of dual-V-T CMOS circuits under challenging delay constraints, with threshold voltages and device sizes as design variables. We show that the presence of interconnect resistance affects the optimum choices of V-T and device sizes, and that ignoring the resistance can lead to highly suboptimal results. We also present criteria for deciding when interconnect resistance should be taken into account.

This paper addresses cycle-true leakage current modeling for static CMOS gates. An approach to leakage power estimation is suggested which deals with some of the issues associated with the complex dynamic behavior of the gate. The paper discusses problems with defining gate leakage power. It then suggests a modeling approach, which separates the static leakage from the dynamic switch and short-circuit power. The model is used to achieve cycle-true leakage power estimation which is important as 20% of the power consumption in the designs of today can be leakage power. The importance of leakage power modeling will continue to grow as leakage power scales exponentially with reduced V/sub T/.

Early and accurate power estimation has become very important to meet the power budget in modern electronics design. In order to achieve early figures on power consumption, functional units have been modeled as black boxes and their respective power consumption has been modeled as a function of signal activity in inputs and outputs. Interconnects, and the associated load capacitances, are accounted for by simply adding the switching power consumption of the interconnect to the estimated power consumption of the functional unit driving the interconnect. Thus, the effects of load capacitance on short-circuit power in the functional units are not considered. The purpose of the present paper is two-fold: first, we put some focus on the review the effects that load capacitance has on short-circuit power. Secondly, we present two methods for interconnect-driven estimation of short-circuit power in state-of-the-art electronics design

This paper addresses low-power circuit design for delay-constrained portions of cutting-edge ICs, in which scaled threshold voltages have made leakage power consumption a major concern. Assuming parameters for a dual-VT 0.10-μm process generation, we analyze two different circuits, using low-VT and high-VT devices, respectively, obeying an identical delay constraint. The power consumption comparison shows that counteracting leakage currents by replacing low-VT with high-VT devices may lead to a rapidly increasing total power consumption. This is caused by an increasing switching power, due to the dramatic sizing required in the high-VT circuit to make it satisfy the delay constraint.

A new interconnect-driven DFT implementation is proposed in this paper. The normal way to implement the DFT is to use the FFT algorithm since it is computationally favorable. However, the increased speed comes at the cost of increased communications which give a higher power consumption. If the DFT algorithm is directly implemented instead, each channel becomes independent of all other channels and consequently communications and hence power consumption are reduced. Other benefits of using the DFT directly are the possibility to calculate a spectrum of any length, not only a power of two, and to have an irregular frequency step between channels. A number of ad hoc processing-element (PE) and system-level solutions are also proposed to reduce the power consumption even further.