This paper presents the design and the measurement results of a high speed A/D converter (ADC or digitizer) developed for radio-astronomy applications and especially for the ALMA (Atacama Large Millimeter Array) project. This monolithic digitizer is implemented in a BiCMOS 0.35 μm SiGe process for high frequency mixed-signal applications. The main characteristics of this circuit are a 2 bits resolution with 3 quantization levels (equivalent to 1.5 bits) with 4 Gsample/s rate, a wide input bandwidth from 2 GHz up to 4 GHz under full Nyquist condition. The adopted digitizer architecture is that of a conventional flash analog to digital converter structure. The overall chip dissipates 652 mW under ± 1.25 V supply and the die area is 5.4 mm2.

Les travaux de cette these portent sur l'etude et la realisation d'un ASIC convertiseur analogique-numerique tres large bande (entre 2 et 4 GHz) fonctionnant a 4 GHz et presentant une resolution de 3 bits. Ce convertisseur est dedie aux applications radio-astronomiques et tout specialement pour le projet d'interferometrie ALMA (Atacama Large Millimeter Array) qui sera implante au Chili des 2007. Le signal capte etant un bruit de statistique gaussienne, la resolution du convertisseur peut etre limitee a quelques bits sans pour autant deteriorer de maniere importante l'information contenue dans le signal analogique. Compte tenu de la frequence d'echantillonage tres elevee, il est necessaire d'utiliser des technologies d'integration tres performantes et des structures de conversion tres rapides. Nous utilisons pour cela une architecture flash implementee dans une technologie BiCMOS SiGe 0,25 [mu]m de la societe STMicroelectronics. Ce systeme fait le lien entre le FrontEnd qui constitue la partie detection du radiotelescope et le correlateur qui effectue la detection et le post-traitement numerique du signal. Le convertisseur est constitue d'un amplificateur adaptateur tres large bande (2 a 4 GHZ), de 7 comparateurs-echantilloneurs utilisant des structures differentielles classiques a charges ohmiques de type CML. Ces comparateurs sont commandes par un amplificateur d'horloge 4 GHz. Le resultat de comparaison est code sur un code Gray 3 bits par un encodeur FDL. Les signaux numeriques sont transmis a l'exterieur de la puce par 3 buffers de sortie en logique LVDS presentant des temps de commutation de l'ordre de 50 ps. Une horloge de test integree permet de realiser des tests de fonctionnalite et de fiabilite sans carte de test.

This paper presents the design details and the measurement results of a high speed A/D converter (ADC or digitizer) developed specifically for radioastronomy applications. This monolithic digitizer is implemented in a SiGe BiCMOS process for high frequency mixed-signal applications. The principal characteristics of this circuit are a 2 bits resolution with 3 quantization levels (or 1.5 bits), a wide input bandwidth front end, 2 GHz up to 4 GHz, and a sampling rate of 4 Gsamples/s (Gsps). The architecture for the design of this digitizer is that of a conventional flash analog to digital structure. The experimental results obtained with our sampler ASIC show sinusoidal input signals are properly sampled for clock rates up to 5 GHz. The overall chip dissipates 975 mW under /spl plusmn/1.25 V supply and the die area is 652 mm/sup 2/.

Abstract We report on the design details and first dynamic tests of high speed analog-to-digital converters (ADCs) with characteristics approaching those desired for the ALMA project. A conventional flash ADC architecture has been adopted with monolithic ADCs implemented in BiCMOS 0.35 μm and 0.25 μm SiGe (Silicon-Germanium) processes. We concentrate here on our 2-bit, 0.35 μm designs and test results, while details on our 3-bit designs and 0.25 μm SiGe technology will be given in another paper. The main features of these 2-bit ADCs are a 4 GHz clock rate, 3 quantization levels, and an input bandwidth from 2 GHz up to 4 GHz. The two chips tested in this work dissipate 650 and 975 mW under 2.5 V supply; the die areas are 5.4 mm and 6.5 mm, respectively.

In this paper, the design details and dynamic tests of a high-speed sampler (ADC or digitizer) are reported. Monolithic digitizer is implemented in a BiCMOS 0.35µm SiGe processes. The features of this ADC are a clock rate of 4 GHz with 3 quantization levels and an input -0.5 dB bandwidth from 2 GHz up to 4 GHz. The adopted architecture for the design of a 2 bits digitizer is that of a conventional flash analog to digital converter structure. The overall chip dissipates 652 mW under 2.5 V supply and the die area is 5.4 mm2.

A new fully integrated clock and data recovery (CDR) topology based on a synchronous oscillator (SO) is presented in this paper. Implemented in CMOS VLSI 0.25 µm technology, the circuit is dedicated to 1 Gbps point-to-point networks. It presents very low jitter measurements : 9.8 and 11 ps rms for respectively PRBS7 and PRBS31 patterns. The circuit exhibits some major advantages versus classical CDR based on PLL and DLL : no external component needed, low consumption and low locking time.

A new fully integrated clock and data recovery (CDR) topology based on a synchronous oscillator (SO) is presented in this paper. Implemented in CMOS VLSI 0.25 µm technology, the circuit is dedicated to 1 Gbps point-to-point networks. It presents very low jitter measurements : 9.8 and 11 ps rms for respectively PRBS7 and PRBS31 patterns. The circuit exhibits some major advantages versus classical CDR based on PLL and DLL : no external component needed, low consumption and low locking time.

This paper presents a monolithic digitizer, implemented in a BiCMOS 0.35 /spl mu/m SiGe process, with 4 Gsps sample rate, 3 quantization levels and an input bandwidth from 2 GHz up to 4 GHz under a full Nyquist condition. The adopted digitizer architecture is that of a conventional flash analog to digital converter structure. The overall chip dissipates 652 mW under 2.5 V supply and the die area is 5.4 mm/sup 2/. This digitizer is developed for radioastronomy applications and especially for the ALMA (Atacama Large Millimeter Array) project.

In this first paper we describe the approach followed to design and experimentally test the high speed and broad band analog-to-digital converters (ADC's or digitizers) required for the ALMA project. Our prototypes are based on monolithic digitizers implemented in a BiCMOS 0.35 or 0.25 μm SiGe process with 3 or 8 quantization levels and 4 giga samples per second rate for an input signal from 2 to 4 GHz under full Nyquist condition. We have adopted a conventional flash converter architecture to design three different 2-bit digitizers and one 3-bit digitizer. The experimental results obtained with our first 2-bit digitizer ASIC show that sinusoidal input signals are properly sampled for clock rates up to 4.9 GHz. The design details and high dynamic range tests of our ADC's will be reported in forthcoming papers. A specific digitizer test equipment providing the auto-correlation and spectral analysis of the digitized signal has been developed to characterize our designs and provide the necessary feedback to the ASIC design team. It includes a broad band noise generator, a demultiplexing unit following the digitizer under test, a 16-lag auto-correlator, and FFT and display units. This equipment will also play a major role at the pre-production stage and for qualification/acceptance at the production stage. We suggest that the demultiplexing scheme developed for the digitizer test equipment could be used as a basis for multi-bit synchronization of the demultiplexed signal in front of the ALMA fiber optic transmitter system.

We report on the design details and first dynamic tests of high speed analog-to-digital converters (ADCs) with characteristics approaching those desired for the ALMA project. A conventional flash ADC architecture has been adopted with monolithic ADCs implemented in BiCMOS 0.35 µm and 0.25 µm SiGe (Silicon-Germanium) processes. We concentrate here on our 2-bit, 0.35 µm designs and test results, while details on our 3-bit designs and 0.25 µm SiGe technology will be given in another paper. The main features of these 2-bit ADCs are a 4 GHz clock rate, 3 quantization levels, and an input bandwidth from 2 GHz up to 4 GHz. The two chips tested in this work dissipate 650 and 975 mW under 2.5 V supply; the die areas are 5.4 mm2 and 6.5 mm2, respectively.