With the rapid development in e-business and technology, enterprises are now facing fiercer threaten and vague opportunity. How to assist enterprises in gaining competitive advantages through technological and managerial innovation has become a crucial issue to the industrial and academic societies. The main objective of IAM International Conference is to provide a venue where business stakeholders, researchers and experts worldwide can share cutting-edge innovative technologies and managerial theories, exchange valuable experience and form collaborative relationships to promote business innovation and management. We believe it is of immense significance to have an opportunity to share the knowledge from all participants.
Optical microphones represent a promising alternative to the conventional capacitive MEMS microphones, especially when aiming at ultra-low noise applications. This paper reports the design and development of a SiP (System-in-Package) digital optical microphone with 71.6dBA SNR in 5×5×2mm3 package with output sensitivity of -21dBFS/Pa. The system concept is introduced, the design and modeling of the main blocks are presented and the measured results are analyzed.
In many companies throughout the chemical process industries, measurement systems play an important role both in determining the final quality of product, but also in allowing a Six Sigma program to achieve breakthrough performance. Many measurement systems are not up to these tasks. In order to understand the effectiveness of measurement systems, Six Sigma uses the measurement indices of %GR&R and P/T ratio as a part of the improvement strategy. Ineffective measurement systems may lead directly to an increase in “the hidden factory”. This hidden factory is quantified by a calculation of a Cost of Poor Quality or COPQ. Examples of the hidden factory caused by ineffective measurement systems are additional processing costs and loss of product value through unnecessary downgrading. This paper initially defines how the measurement system is a part of the hidden factory. This paper will comment upon the basics of %GR&R and P/T ratio, will highlight the usage of Minitab to perform these analyses, will show examples of measurement systems in industrial applications, and will give suggestions on improving the measurement systems of an organization. The key application from this work is to think of a measurement system as a process, not unlike any manufacturing process. Using the Six Sigma thinking, any process may be studied as a box with inputs and outputs. Study must be done to link poor measurement systems with poor manufacturing and inevitably poor financial performance. Black Belt and Green Belt project work can begin to improve the occasional measurement system. They cannot work alone. It will take a structured approach of evaluating performance of systems (measurement and sampling) correctly, and then developing a systematic procedure to improve performance. This system includes specific training, focused improvement roadmaps, and a project system similar to the system in Six Sigma organizations. The Hidden Factory The Hidden Factory concept is one that is taught early in the Six Sigma course work. It is that area of any process in which rework and non-value exists. If this area is cleaned, a large amount of the Cost of Poor Quality or COPQ of a process is also removed. Tangible Hidden Factory issues include non-reworkable or scrap materials (materials that have lost their product value in processing), over-processed materials (materials processed with non-optimal yields and utilities), and over-analyzed materials (materials that are analyzed inprocess even though the capability is high). The figure below describes the Hidden Factory. In a laboratory setting, the hidden factory also exists. Here the implication of the Hidden Factory is in higher laboratory costs directly and in higher production costs indirectly. The Hidden Factory in a measurement system includes incapable measurement systems (purchased equipment that is incapable and unusable), repetitive analysis (measures that need to be repeated multiple times to achieve usable results, both process and measurement related), and variation issues (various noise issues that produce values that deliver unclear messages to production). The figure below describes this Measurement System Hidden Factory. Inputs Operation First Time Correct Inspect OK
In this tutorial an overview on radiation effects on semiconductor components will be provided under the perspective of CMOS design to mitigate hard errors like latch-up or gate rupture and soft errors (bit upsets and transients). The main radiation hardening techniques, both at circuit and layout levels, will be described with a focus on standard cells, memories (SRAMs and NVMs) and analog components (ADCs and DACs). Testing techniques under irradiation to verify effective hardness suitable for space applications will be described for TID (Total Ionizing Dose with Cobalt 60) and SEE (Single Event Effects with Heavy Ions)
This work presents a low-power, low-temperature-coefficient (TC), digital-friendly RC relaxation oscillator (RxO) for energy-constrained Internet-of-Things (IoT) applications. Implemented in a 22nm CMOS technology that offers only PTAT resistors, the proposed swing-adaptive scheme compensates the first-order TC within the RC stage. Additionally, a clock-gated discrete-time comparator (DT-CMP) scheme is adopted to relax the trade-off between power efficiency and TC. The prototype RxO is measured to have a reference frequency of 700kHz with a TC of 12. $5\mathrm{p}\mathrm{p}\mathrm{m}/{}^{\circ}\mathrm{C}$ (from -$40{}^{\circ}\mathrm{C}$ to 85°C), consuming 760nW with a power efficiency of 1.086nW/kHz.
Advanced CMOS process technology offers the prospect of digitization and software abstraction of the radio access network (RAN) with significant benefits in power, cost, performance, and the ability to create an innovation platform hosting $3^{\mathrm{r}\mathrm{d}}$ party applications generating new revenue streams for the mobile network operator (MNO). As 5G/6G radio spectrum and occupied radio bandwidths continue to expand, the RF performance and digital compute requirements increase exponentially. However, such performance enhancements must be achieved without increasing power consumption, due to environmental and opex considerations as well as mechanical-thermal constraints. This paper will discuss paths forward to addressing these challenges in the areas of system architecture, compute optimisation, integration, and process scaling.
This paper presents a Common Mode Transient Immunity (CMTI) enhancement circuit for transformer based galvanically isolated gate drivers with a negative-Gm oscillator. Regardless of the isolation method or structure, the communication path is susceptible to CMTI events due to the inherent parasitic capacitance. The proposed CMTI enhancement concept prevents false turn-OFF events during negative transients by activating a timer-based current source, which maintains the negative-Gm oscillator active. The CMTI enhancement circuit was verified by means of simulations and integrated in a 0.25 $\mu \mathrm{m}$ CMOS technology as part of a galvanically isolated gate driver. Comparative experimental results with the CMTI enhancement circuit disabled and enabled demonstrate increased resilience against negative transients. The proposed solution achieves Common Mode Transient Immunity levels between 1 kV and 150 $\mathrm{k}\mathrm{V}/\mu \mathrm{s}.$
This paper introduces a backscattered BLE5 transmitter for low-cost single-antenna green systems solely powered by mm-scale harvesters. Peak power reduction to 10.6 $\mu \mathrm{W}$ is achieved while enabling BLE-compliant spectral mask up to the maximum allowed backscattered power for range extension. Peak power is reduced via an approximate GFSK modulator architecture based on a non-uniform self-sampling digitally controlled oscillator (DCO) with period pruning/clustering, in place of a power-hungry Gaussian filter and PLL used in conventional GFSK modulators. A 180-nm testchip shows 97-m range with commodity receiver at 4X power and 3X range improvement with respect to prior art.
This paper presents a 58-64 GHz FMCW radar transceiver for vital sign measurements based on high integer N frequency multiplication. It is implemented in CMOS 45nm RFSOI technology. The FMCW chirp slope can be increased up to 30 $\mathrm{G}\mathrm{H}\mathrm{z}/\mu \mathrm{s}$ thanks to the high multiplication factor of 30. The phase noise is as low as-108 dBc/Hz. Aggressive chirp duty cycling (<300ns start-up time) enables a very low power consumption of 12.3 mW for 100 KHz repetition rate. The radar is used to demonstrate down to 10 $\mu \mathrm{m}$ displacement measurement using 2 GHz FMCW bandwidth to detect human breath and heart rate.
In this paper we demonstrate ultra-high sensitivity silicon nanowires pH and protein sensing on the same Silicon nanowire array platform by using a constant current method and monitoring the drain voltage as function of analyte concentration. The injected current levels allow choosing the most appropriate electrical sensing conditions, which in our sensors corresponds to the moderate inversion region, providing the best tradeoff between sensitivity, stability, and power consumption. This method appears to be the most appropriate for real-time continuous measurements of biomarkers in human biofluids. Using real human sera samples, to mimic the composition of interstitial fluids (ISF), we demonstrate pH sensing in the physiopathological range from 6.5 to 8. An excellent accuracy in this complex matrix, with a maximal error as low as 0.92% (0.07pH unit), was achieved in constant-current method at optimal current levels (1.71% for top-gate). By using different pools of human sera, with different total protein content, we show that patient to patient protein content does not influence the sensors’ performance to pH. On the same sensing platform we develop and demonstrate a proof of concept for protein sensing that benefits from the signal amplification and improved SNR obtained with the proposed method by showing C-Reactive protein detection (CRP) in PBS 0.1X. The reported results aim to establish the foundations for the development of a wearable and continuous biosensor that can jointly detect pH and CRP in human interstitial fluids using silicon nanowires.
This paper presents in-pixel and near-pixel processing circuit techniques for multi-mode processing CMOS vision sensor. The new design includes a checkerboard patch-based pixel circuit and column-shared frame difference processing circuits that detect a patch-level temporal change and generate lb event signal. In-pixel time memory circuit is proposed to process a temporal derivative of the event in both area and power efficient way. The 324× 252 vision sensor is implemented in 0.18 $\mu$m CMOS process and consumes 4.79 $\mu$W @12.5fps showing FoM of 42.2pJ/pix. frame in the patch mode operation for frame difference-based motion detection and temporal derivative generation.
This paper describes a coherent UWB receiver architecture based on a quadrature hybrid correlation (QHC) method to significantly reduce the digital correlation power of the conventional standard-compliant UWB receiver. The proposed QHC receiver front end employs analog correlation, two-step synchronization, and time-interleaved (TI) sampling methods for low-power synchronization and demodulation. A code-mismatch-evaluation method is introduced for localization, and a ternary analog correlator is proposed for noise mitigation and high-quality computing. The receiver supports preamble, scrambled timestamp sequence (STS) and burst position modulation (BPM). The proposed 8GHz receiver implemented in 65nm CMOS consumes 17.3mW at 0.98Mbaud/s with a sensitivity of -88dBm at a BER of 10-3 and -24dBm blocker tolerance, enabling the lowest baseband power among standard-compliant UWB receivers. In the STS field, the receiver achieves an RMS ranging error of 1.9cm.
This paper presents a 4.8-to-5.6 GHz timeinterleaved multi-reference PLL with sub-20fs jitter. The reference clocks are aligned with the time-interleaved feedback clocks produced by the multi-phase divider. Fabricated in 65-nm CMOS technology, the prototype achieves 16.1-fs jitter integrated from 10kHz to 40MHz at 4.8-GHz carrier, and consumes 83mW. To the best knowledge of the authors, it is the lowest jitter PLL in CMOS/SiGe technology reported so far.
Homomorphic Encryption (HE) is used to protect sensitive client data during offloaded compute on a potentially untrusted server. Unfortunately, the computational intensity of HE operations quickly depletes the limited resources on IoT clients. Thus, we present an energy-efficient silicon implementation of encryption/decryption in the Brakerski-Fan Vercauteren HE scheme. To support meaningful applications, including several machine learning workloads, we optimize for fixed parameters N =4096 and lo$g_{2}$q =109 through pipelining, multi-level parallelism, and efficient memory accesses. At an energy-optimal operating point of 60MHz and 0. 64V our chip, fabricated in a 2Snm bulk planar CMOS process with an accelerator core area of 1.69 m$\mathrm{m}^{2}$, consumes 10.33 $\mu$J/encryption. Ultimately, this work enables IoT clients to participate in privacy-preserving offloaded compute using client-aided Homomorphic Encryption.
The cryogenic electronic interface for quantum pro-cessors requires cryo-CMOS embedded memories that cover a wide range of specifications. The temperature dependence of device parameters, such as the threshold voltage, the gate/subthreshold leakage, and the variability, severely alters the memories’ performance between room temperature (RT) and cryogenic temperatures (4.2K). To assess the best memory design for a given application, this paper benchmarks three custom DRAMs and a custom SRAM in 40-nm CMOS at 4.2 K and RT, e.g., identifying that, while the SRAM is more power efficient for moderate-to-high speeds at RT, the 2T DRAM performs better than SRAM and 3T DRAMs at 4.2 K.
The presented IEEE 802.15.4z IR-UWB transmitter is aimed at providing long battery life and compatibility with international standards. Thanks to the optimized pulse shaper and pulse combiner, the sidelobe power is <-29dBc, required for ETSI compliance at 6.5GHz. Extensive duty-cycling in the RF oscillator and the TX enables a low power consumption of 380μW, which is 10× better than state-of-the-art low side-lobe IEEE 802.15.4z transmitters.
An SRAM-based mixed-signal current-domain Compute-In-Memory (CIM) macro is presented that extracts low-dimensional digital features from high-dimensional analog inputs (Analog Feature Extraction, AFE). A prototype AFECIM chip in 28nm CMOS extracts 16-channel (S-bit) digital features from 128-channel analog input $(8\times$ dimension reduction). The chip consumes 71.25 mW at a throughput of 600 Mega-Sample-Per-Second (MSPS, a sample is 128-analog input) achieving 43.7 TOPS/W peak energy efficiency and 120 $TOPS/mm^{2}$ peak computation density.
This paper presents a novel 3D image sensor based on single-photon avalanche diodes (SPADs) with asynchronous readout and adaptive pixel sensitivity. The proposed sensor architecture is capable of acquiring both intensity and depth information about the scene in an efficient manner. The sensor pixel sensitivity is adaptively adjusted based on the illumination of the scene, optimizing the readout channel bandwidth. The asynchronous readout scheme reduces the readout time and data rate since information of meaningless pixels is not conveyed off-chip, allowing the sensor to operate at a high frame rate and reducing the massive data throughput of conventional SPAD-based sensors.
