This paper presents a hybrid Phase-Locked Loop (PLL) architecture that enhances the robustness of conventional analog topologies against two-point modulation mismatches. Behavioral time-domain simulations demonstrate over 50% improvement in Error Vector Magnitude (EVM) while preserving compliance with spectral masks requirements. The proposed architecture provides a flexible solution capable of supporting high data rates without compromising compatibility with legacy operation modes.

This paper introduces a dual-loop frequency synthesizer that synergizes the scalability of an all-digital phaselocked loop (AD-PLL) with the high precision of an analog PLL, targeting the demanding specifications of Internet of Things (IoT) applications. Traditional AD-PLLs suffer from quantization noise due to limited time-to-digital converter (TDC) resolution, whereas analog PLLs offer low jitter but compromise on reconfigurability and silicon area. In the proposed design, the ADPLL achieves a coarse frequency lock within approximately $\mathbf{1. 0} \boldsymbol{\mu} \mathbf{s}$, followed by fine frequency refinement via the analog loop, reaching full lock in $3.3 \mu$ s. For frequency hopping scenarios, this dual-loop architecture supports rapid relocking in $1.6 \mu ~\mathrm{s}$, satisfying Bluetooth Low Energy (BLE) channel-switching timing requirements. Implemented in 18 nm FD-SOI CMOS technology, the synthesizer attains jitter below 2 ps while consuming power in the $\mu \mathrm{W}$ to mW range. Compared to existing hybrid approaches, the sequential dual-loop strategy effectively eliminates loop interference, minimizes loop filter area through a low-Kvco design, and achieves an optimized balance among speed, noise, and power consumption, positioning it as a compelling solution for next-generation low-power wireless transceivers.

Future wireless systems are expanding toward multi-gigahertz (GHz) bandwidths and sub-terahertz (THz) frequencies. Conventional solutions struggle with high sampling rates, strong nonlinearities, and the diminishing efficiency gains of analog circuits in complementary metal-oxide-semiconductor (CMOS) technologies. Wideband radio-frequency (RF) architectures require a new signal representation and processing paradigm to address these challenges, enabling energy-efficient wideband access and linearization. The Walsh sequency domain offers such an opportunity: its orthogonal basis enables highly parallel and energyefficient wideband operations, reducing RF signal-processing complexity while remaining fully compatible with CMOS technologies. Operating directly in the Walsh domain allows compact implementations of RF conversion, channelization, and nonlinear compensation. These capabilities have been experimentally demonstrated through proof-of-concept integrated circuits in CMOS fully depleted silicon-on-insulator (FDSOI) technologies, including GHz-range RF conversion, digital pre-distortion (DPD), and channel-aggregation techniques. Furthermore, a Walshnative end-to-end wireless autoencoder shows improved robustness to amplifier nonlinearities while benefiting from reduced sampling requirements. Walsh-based RF processing opens a new design space for multi-GHz bandwidth, energy-efficient, and hardware–algorithm co-design in next-generation artificial intelligence (AI)-assisted communication systems.

FD-SOI technology offers degrees of freedom in analog and digital circuit design through back-gate biasing. This work investigates the influence of back-gate voltage and layout on the temperature sensitivity of transistors this, through both simulation and measurement. A temperature-compensated voltage reference, from a previous work of ours, is employed as a test vehicle. We compare three layout strategies to evaluate spatial effects on temperature drift. The measurement campaign, conducted using a dedicated datalogger and temperature-controlled setup, confirms simulation about temperature-induced variations. The results underline the importance of careful back-gate management in FD-SOI for robust design.

This paper presents the first experimental demonstration of fully Walsh-based wideband converters for Radio Frequency Front-End (RFFE) architecture implemented in 28 nm FDSOI CMOS technology. The system integrates a Walsh-based RF digital-to-analog converter (WDAC) and a Walsh-based RF analog-to-digital converter (WADC) designed for digital predistortion (DPD) applications. The WDAC achieves an instantaneous bandwidth of 4.7 GHz with an energy efficiency of 0.57 pJ/bit. The WADC achieves a 2.5 GHz bandwidth while consuming only 4 mW. The experimental demonstration showcase efficient wideband signal processing in the Walsh domain and highlights its potential as a promising paradigm for future low-power, high-throughput wireless transceivers, offering both wideband capabilities and a new order of scale energy efficiency.

This brief proposes a wideband Power Amplifier (PA) integrated in 28nm FD-SOI CMOS technology dedicated to sub-6 GHz 5G with controlled PAEmax based on a variable harmonic load across its operating bandwidth. The PA achieves a gain between 31 and 34 dB, a $P_{sat}$ from 20.5 to 22 dBm in the operating bandwidth from 2.9 to 6.1 GHz. Thanks to the PAE control, a PAEmax between 27 and 35% is achieved along the entire operating bandwidth. Modulated 5G-NR FR1 signal measurements are performed with a Walsh-based DPD using an intra-band carrier aggregation scenario to showcase the PA robustness for contiguous carriers. For the first time to the best author's knowledge, PAEmax control is demonstrated over a relative bandwidth of 71%.

This paper presents the first experimental demonstration of a fully Walsh-domain Radio Frequency Front-End (RFFE) architecture implemented in 28nm FDSOI CMOS technology. The system integrates a Walsh-based RF digital-to-analog converter (WDAC) and a Walsh-based RF analog-to-digital converter (WADC) for digital predistortion (DPD) purpose. The WDAC achieves an instantaneous bandwidth (BW) of 4.6875 GHz with an energy efficiency of 0.38 pJ/bit. The WADC supports a 2.5 GHz BW and consumes only 4 mW. This experimental demonstration showcases wideband and power-efficient signal processing and highlights the potential operating entirely in the Walsh basis as a compelling approach for future low-power, high-throughput wireless systems, combining both energy efficiency and wideband performances.

This paper investigates a voltage reference circuit that incorporates an equivalent MOSFET, which adjusts the threshold voltage and its temperature coefficient using a Proportional To Absolute Temperature (PTAT) voltage generation circuit. In previous designs, the relationship between the drain current ID and the gate-source voltageVGS was derived based on the threshold voltage Vth from the gradual channel model of MOSFETs. However, this method led to discrepancies between theory and simulation. We propose a new approach where the ID - VGS characteristics are modeled using simulation data from a single NMOSFET, fitted to a general quadratic function. This model significantly reduces the error between theoretical calculations and simulation results. Additionally, the temperature coefficient of the reference voltage Vref is improved from 498 ppm/K to 32 ppm/K.

This paper discusses the development of a new topology voltage reference in Fully Depleted Silicon-On-Insulator (FD-SOI) technology. The voltage reference described in this paper is based on threshold voltage subtraction techniques, PTAT and CTAT voltage addition and transistor's back-gate biasing in 28nm FD-SOI technology. It has a 860mV output and achieves a performance of 73.5ppm/degrees C (T=-50 degrees C to 150 degrees C) under a supply voltage of 1V.

This paper presents a novel current-steering RF DAC design in 28nm CMOS FDSOI technology. The architecture enhances linearity, minimizes energy consumption, and ensures scalability for high-frequency applications. It includes a modified differential pair with neutralizing capacitors, cascode transistors, and body-biasing to mitigate charge injection and Miller effects. The low-power design enables high interleaving capacity, suitable for interleaved Digital-to-Analog Converters (DAC). Simulation results show an 8GHz maximum frequency and 2.504mW power consumption, making it a promising candidate for efficient high-performance RF applications.

Exploring millimeter-wave bands presents fresh opportunities for new high data rates communication standards, yet confronts technological challenges like power amplification. Digital predistortion (DPD) offers a solution to enhance the linearity of the amplification while keeping high efficiency. Since Envelope Transient simulations (ET) are time-consuming during circuit design, designers often restort to experimental DPD verification instead. This paper proposes two co-simulation workflows to simulate modulated signals on Integrated Circuits (IC) Power Amplifiers (PA) with an application of DPD. Simulation results indicate that the computational modeling of power amplifiers enables 99% faster schematic and post-layout (PLS) ET simulations, reducing the time needed from months to minutes while maintaining comparable output accuracy.

This paper presents an innovative technique to reduce the temperature dependency of transistors. This technique relies on Back-Gate and parasitic diodes biasing, exploiting the Complementary To Absolute Temperature (CTAT) behavior of diodes' threshold voltage. Ideas and work presented in this paper are based on the Fully Depleted Silicon-On-Insulator (FD-SOI) technology. The proposed technique is validated through a test bench mimicking real-world conditions. The results show that the proposed technique can effectively reduce temperature dependency.

A VCO was designed in 28-nm FD-SOI for robustness against aging mechanisms such as Time Dependent Dielectric Breakdown (TDDB) and Hot Carrier Injection (HCI). A high-swing class-C oscillator featuring a control circuit was chosen as the base of the architecture. A cascode topology was adopted to improve reliability and a local capacitive feedback was used to improve transductance. A combination of design and data analysis on aging effects of the technology contributed to the design of a robust and suitable device for space applications with state-of-the-art performances. The VCO has a frequency range of 10-11.7 GHz, a tuning range of up to 16.4%, a power consumption down to 4.88 mw, 0.073 mm2of area and achieves a phase noise of down to -114 dBc/Hz, a FoM of 185 dBc/Hz and a FoMT of 190 dBc/Hz at 1 MHz offset, regardless of the two transistors used instead of just one to improve robustness.

A Proof-of-Concept (PoC) of a wideband Power Amplifier (PA) with controlled efficiency based on second har-monic matching is proposed in this paper. The context of carrier aggregation in the 5G standard needs wide operating bandwidth with high Power Added Efficiency (PAE). Thus, the output network uses harmonic processing techniques to control the PAE over the bandwidth (BW) from 0.65 to 1.5GHz. The gain is between 9.2 and 12.2dB, $P_{sat}$ is between 24.2 and 27.2 dBm, and the $\text{PAE}_{\max}$ is between 42.5 % and 57 % with a best improvement of 16 points at 1.4GHz.

Millimeter-wave hands open new bands of interest for ultra-high-speed wireless communications, but face technological bottlenecks such as power amplification. Working near the maximum oscillation frequency of the transistor leads to low intrinsic gain and low efficiency. Digital predistortion (DPD) achieves a higher power efficiency without degrading linearity. This paper presents a co-simulation workflow to design jointly DPD and the power amplifier (PA) in order to reach the optimum performances in linearity and power-added efficiency (PAE). The design of a PA at a center frequency of 142 GIIs using the CMOS 28nm FDS01 technology from S'IMicroelectronics demonstrates how the design flow can take into account continuous wave (CW) and modulated signal simulations with and without DPD. The linearity performance is highlighted on the adjacent channel power ratio (ACPR) with an improvement of 4dB on an OFDM signal with 800 MHz bandwidth.

This paper presents a transceiver for an Ultrasonic Intra-Body Area Network (UIBAN) enabling regular monitoring of low data rate bio-signals. The modulation scheme is Binary Phase Shift-Keying (BPSK) because of its superior energy efficiency compared to the other binary modulations. Therefore, a BPSK detector composed of a single D flip-flop is proposed. The carrier frequency is 1 MHz and the bit rate is 7.8125 kbits/s. The integrated circuit (IC) was designed in the 0.35 μm CMOS technology from AMS. The complete transceiver was measured with 2 2mm diameter ultrasound transducers. The measured Bit Error Rate (BER) was 1.8 × 10-3 and 1.3 × 10-2 over a distance of 3.1 cm and 17.5 cm in castor oil, although subjected to many reflections. This is, to the authors’ knowledge, the highest measured communication distance with two ultrasonic transducers of a volume lower than 10mm3 in an environment similar to that of the human body.

This paper presents the design and measurement results of an sub-half-mW frequency synthesizer, composed of a multiplying delay-locked loop (MDLL), which reduces the phase noise of a standard ring oscillator. The proposed circuit takes advantage of the low-jitter and high loop bandwidth characteristic of the MDLLs, and has the particular feature of being able to lock to any external reference frequency between 50 and 100 MHz. It is known from the previous state-of-theart implementations that the reference spur degrades the output spectrum. In this work, an ultra-low-power spur reduction circuit is proposed to improve the spectral purity of the output spectrum, achieving -47.2dBc of spur rejection, measured for 10 chips. For 456 $\mu$W of power consumption, 2.5 ps of RMS jitter, the proposed solution presents a Figure of merit (FoM) of -235dB, being suitable for ultra-low-power IoT applications.