In this study, we have fabricated nanometer-scale channel length quantum-well (QW) metal-oxide-semiconductor field effect transistors (MOSFETs) incorporating beryllium oxide (BeO) as an interfacial layer. BeO has high thermal stability, excellent electrical insulating characteristics, and a large band-gap, which make it an attractive candidate for use as a gate dielectric in making MOSFETs. BeO can also act as a good diffusion barrier to oxygen owing to its small atomic bonding length. In this work, we have fabricated In0.53Ga0.47As MOS capacitors with BeO and Al2O3 and compared their electrical characteristics. As interface passivation layer, BeO/HfO2 bilayer gate stack presented effective oxide thickness less 1 nm. Furthermore, we have demonstrated In0.7Ga0.3As QW MOSFETs with a BeO/HfO2 dielectric, showing a sub-threshold slope of 100 mV/dec, and a transconductance (g(m, max)) of 1.1 mS/mu m, while displaying low values of gate leakage current. These results highlight the potential of atomic layer deposited BeO for use as a gate dielectric or interface passivation layer for III-V MOSFETs at the 7 nm technology node and/or beyond. (C) 2014 AIP Publishing LLC.

RRAM devices utilizing a filamentary conduction mechanism have attracted significant attention due to their unique scalability, excellent switching speed, and endurance. On the other hand, the RTN-like read current instability and cycle-to-cycle variability observed in these devices are still a concern from operational standpoint. In this study, we investigate the impact of switching conditions on HRS/LRS read instability/noise and variability by employing a fully automated measurement setup, which is capable of effectively collecting low resistive state (LRS) and high resistive state (HRS) read current values during the cycling under different AC SET/RESET conditions,. Analysis of the read current variati on over a statistically significant number of switching cycles allows extracting the parameters of the distributions of variability and reading instability amplitudes in both HRS and LRS. We discuss physical mechanisms for the LRS and HRS instability explaining how it is impacted by scaling of the operating current.

This paper reports tri-gate sub-100 nm In0.53Ga0.47As QW MOSFETs with electrostatic immunity of S = 77 mV/dec., DIBL = 10 mV/V, together with excellent carrier transport of gm, max > 1.5 mS/μm, at VDS = 0.5 V. This result is the best balance of gm, max and S in any reported III-V MOSFETs. In addition, extracted compact model parameter including (μ0 = 760 cm2/V-s and peak vx0 = 1.6×107 cm/s) indicate that InGaAs Tri-Gate MOSFETs would be a viable pathway to sub-10nm technology node.

A semiempirical model that can simulate dc and pulse (ac) characteristics of filament-type HfOx-based resistance change random access memory (ReRAM) devices has been developed. Time-dependent device characteristics, because of the dynamic change in the filament size, were emulated using a modified ion migration model. This model describes the difference between SET and RESET operations using a current crowding effect This model is a semiempirical model that can simultaneously match both dc and ac characteristics of HfOx-based ReRAM devices.

Resistive switching (RS) phenomenon in the HfO2 dielectric has been indirectly observed at device level in previous studies using metal-insulator-metal structures, but its origin remains unclear. In this work, using the enhanced conductive atomic force microscope (ECAFM), we have been able to obtain in situ direct observation of RS with nanometric resolution. The ECAFM measurements reveal that the conductive filaments exhibiting the RS are primarily formed at the grain boundaries, which were shown exhibiting especially low breakdown voltage due to their intrinsic high density of the oxygen vacancies.

As the MOSFET gate lengths are scaled down to 50 nm or below, the expected increase in gate leakage will be countered by the use of a high dielectric constant (high K) material. The series capacitance from polysilicon gate electrode depletion significantly reduces the gate capacitance as the dielectric thickness is scaled down to 10 Å equivalent oxide thickness (EOT) or below. Metal gates promise to solve this problem and address other problems like boron penetration and enhanced gate resistance that will have increased focus as the polysilicon gate thickness is reduced. Extensive simulations have shown that the optimal gate work-functions for the sub-50 nm channel lengths should be 0.2 eV below (above) the conduction (valence) band edge of silicon for n-MOSFETs (p-MOSFETs). This study summarizes the evaluations of TiN, TaSiN, WN, TaN, TaSi, Ir and IrO2 as candidate metals for dual-metal gate CMOS using HfO2 as the gate dielectric. The gate work-function was determined by fabricating MOS capacitors with varying dielectric thicknesses and different post-gate anneals. The metal-dielectric compatibility and thermal stability was studied by annealing the stacks at different temperatures. The gate stacks were characterized using TEM, SIMS and X-ray diffraction. Based on workfunctions and thermal stability, TaSiN and TaN show most promise as metal electrodes for HfO2 n-MOSFETs.

The bottle neck of ReRAM (Resistive RAM) for post-NAND storage application is high operational current. Herein, we report a method to acquire low operational currents from a hetero structure ReRAM (AlOx/TiOx). The mechanism study of the hetero structure ReRAM reveals that the AlOx layer as a tunnel barrier is critical for switching, and thus switching parameters are governed by the properties of the AlOx layer. By tuning tunnel oxide properties along with adopting 5 nm sized “Dash BE”, operational currents of ≤10 μA have been achieved from this hetero structure device.

In TANOS stuctures in retention, the major decrease in the programmed threshold voltage is found to be caused by the Vt sensing (IdVg measurements) rather than by intrinsic charge loss (when no bias is applied). This Vt decrease can be understood within the process of the temperature-activated charge transport through the Al2O3 blocking oxide. The charge loss can be minimized when Vt sensing time is decreased down to micro seconds. Blocking oxides engineered by adding a thin SiO2 layer at the SiN/AlO interface demonstrate significant suppression of the charge loss.

This paper reports on a scalable and simple gate-first integration option for manufacturing the high-k/metal gate CMOS transistors targeting sub-32 nm LSTP applications: Vt < plusmn 0.45 V (at Lg = 60 nm) at EOT les 1.4 nm, with 105 times Jg reduction compared to SiO2. This scheme integrates several simplifications and improvements for the first time: single metal gate material, single channel material, dual selective LaOx / AlOx cap removal without lithographic overlay tolerances issues and optimized HfSiON for LSTP leakage targets.

The intent of this research is to understand the role of interface chemistry on the effective work function and device characteristics of metal gate electrodes on hafnium dioxide (HfO2) gate dielectrics in metal oxide semiconductor field effect transistors. Since multiple factors, including crystal structure, preferred orientation, chemical composition, interface bonding, and reactions or interdiffusions, impact the effective work function, solid-solution carbonitrides of tantalum (TaCxN1−x) have been studied in an attempt to isolate the role of interface chemistry on the effective work function. Tantalum carbonitride films have been carefully deposited with similar Ta∕(C+N) ratios to understand how the substitution of N for C on the octahedral interstice in a face-centered-cubic tantalum lattice impacts device performance. Results indicate that the effective work function and device threshold voltage are reduced when the less electronegative carbon atom is substituted for the more electronegative nitrogen atom. This result is in qualitative agreement with the known relationship between metal electronegativity and effective work function and demonstrates the important role that sublattice elements in binary metal compounds have on the effective work function of the gate electrode.

Factors responsible for the undesirably high values of positive-channel (p-channel) threshold voltage (Vt) in high-κ metal oxide semiconductor transistors are investigated. In silicon/silicon dioxide/hafnium dioxide/metal gate transistors an anomalous nonlinear relationship between the equivalent oxide thickness (EOT) and Vt occurs when the silicon dioxide (SiO2) interface layer is sufficiently thin (<2.3 nm). The deviation from the expected EOT versus Vt behavior is shown to be related to processing temperature, metal work-function, substrate doping type, and thickness of the high-κ material. This result, coupled with charge trapping measurements on samples with different SiO2 interface layer thickness, suggests that the loss of negative fixed charge via the tunneling of trapped electrons to the substrate is a possible explanation for the elevated p-channel Vt.

The empirical relationship between electronegativity and effective work function is applied to a diverse set of multielement electrode materials on hafnium dioxide (HfO2) gate dielectrics. To accommodate the multi-element nature of metal gate electrodes the group electronegativity of the metal was calculated from the geometric mean of electronegativity with respect to the volume stoichiometry of the constituent elements. Results show a reasonable linear fit that provides guidance for the selection of metal gate electrodes on HfO2. The group electronegativity concept is also extended to work function engineering via dielectric capping materials. The electronegativity trends provide insight into the relative charge neutrality levels of candidate dielectric capping materials and their subsequent impact on the metal effective work function.

A generalized reliability model of BTI is presented where it is shown that gate stacks with similar interfacial layer lie on the same NBTI vs. E-field universal curve and those with similar bulk layer lie on the same PBTI vs. E-field universal curve. From these universal curves, an optimal gate stack can be derived for which NBTI=PBTI