The paper presents the first comprehensive analysis of the electrical contact topologies to two-dimensional (2D) transition metal dichalcogenide (TMD) semiconducting materials by employing ab-initio density functional theory (DFT) and non-equilibrium Green’s function (NEGF) formalisms. Using Landauer’s equations, comprehensive numerical models for contact resistance (R C ) of these contact configurations have been derived and subsequently extended to develop the first closed-form expressions for contact resistance to 2D materials (2DM) in these configurations. The comprehensive modeling framework, which includes boundary and interface scatterings, Fermi level pinning (FLP) through metal induced gap states (MIGS), terminated edge states, and surface reconstructions due to interface bonding, the effect of FLP quenching through the presence of a van der Waals (vdW) gap, and the physics of carrier transport across such an interface, is intended for designing 2D FETs with minimal R C and extracting from experiments the accurate Schottky barrier (SB) height to model realistic 2D-FET device/circuit performance. Hybrid contacts with sufficient (~2 nm) metal-2DM overlap are found to be optimal, and carrier (doping) concentrations and SB height needed for satisfying IRDS requirements have been identified.

A micromagnetic study of the thermal stability and magnetization switching by spin-polarized current in Perpendicular Magnetic Tunnel Junctions comprising a four-layer stack of free layer, reference layer, and synthetic antiferromagnets is presented. It is demonstrated that the minimal energy path (MEP)—related to the thermal stability of the system—does not necessarily follow the same trajectory as the current-induced switching. The MEP can be by uniform rotation (UR) or by domain walls (DWs), whereas the current-induced switching can be by UR, DWs, or bubble formation depending on geometrical and stack parameters. The bubble formation is further affected by the direction of switching, i.e., parallel to antiparallel vs antiparallel to parallel switching. We demonstrate the existence of different regimes where the energy barrier and the figure of merit, defined as a ratio between the energy barrier and switching current, show characteristic dependencies and even optimum points depending on the device diameter and the stack parameters. The presented results may explain recent experiments.

This paper focuses on the study of Co/Low-k dielectric TDDB (Time Dependent Dielectric Breakdown) in Intel’s 10nm process technology. We demonstrate that 36nm/40nm pitch Cobalt interconnects with Low-k dielectric successfully meet our technology TDDB reliability goals. Furthermore, extensive study of the leakage mechanisms, including TCAD modelling, indicates that the dominant conduction mechanism in Co/Low-k is Schottky Emission (SE), with some contribution from Fowler Nordheim (FN) at high E-field. Characterization using Triangular Voltage Sweep (TVS) with Constant Voltage TDDB does not show metallic ion-related peaks. These results support that Co/Low-k interconnect reliability is limited by the intrinsic breakdown of the dielectric material, with no evidence of Co ion migration in Intel 10nm process.

This paper presents key features of MRAM-based non-volatile memory embedded into Intel 22FFL technology. 22FFL is a high performance, ultra low power FinFET technology for mobile and RF applications with extensive high voltage and analog support, and a high level of design flexibility at low cost 1 . Embedded NVM technology presented here achieves 200°C 10-year retention capability combined with>10 6 cycle endurance and high die yield. Technology data retention, endurance and yield capabilities are demonstrated on 7.2Mbit arrays. We describe device-level MTJ characteristics, key integration features, cell characteristics, array operation specifics, as well as key yield milestones.

Spin-transfer-torque (STT) random access memory (STTRAM) is considered to be one of the promising candidates for a non-volatile memory for improved scalability and access speed. Write error rate (WER) in an STTRAM is the probability that the free layer magnetization of the STTRAM bit does not flip when a write current is applied because of random thermal fluctuations. The WER needs to be below a certain acceptable limit for reliable write operation. Previously, WER have been studied using Fokker-Planck (FP) calculations for perpendicular bit [1] and using Landau-Lifshitz-Gilbert (LLG) simulations for the magnetization dynamics including a random thermal magnetic field and an STT term, for an in-plane bit with and without perpendicular magnetic anisotropy (PMA) [2]. These studies however assumed the free layer magnetization to be a macrospin, thereby neglecting the spatial variation in spin across the free layer (micromagnetic effects). Several important experimental observations related to WER in STTRAM have, however, been attributed to spatially varying spin-texture in the free layer magnet, for example, sub-volume excitations [3] and higher order spin wave modes related to branching of WER [4, 5].