In the field of system-level diagnosis, traditional research focuses on diagnosabilities under specific constraints, which reflect network reliability. Networks with higher diagnosability are often adopted in supercomputers, Network-on-Chip (NoC), and other applications. However, in decentralized parallel computing systems, diagnosability is limited by faulty vertex cuts, leading to undiagnosable subnetworks when the isolated part grows large. To address this, we propose a two-stage plan for global reliable diagnosis by combining the Self-Comparative (SC) model with the g-good-neighbor property, ensuring every vertex can be diagnosed with high accuracy. Six algorithms are developed to implement the model and support diagnosis for g >= 2. Furthermore, we code a simulator to evaluate the plan's effectiveness. Simulation results demonstrate satisfactory performance in terms of diagnostic coverage and efficiency. All source codes are provided via a GitHub link for public access and reproducibility. This work offers a novel perspective for enhancing network-level fault tolerance. (c) 2025 Elsevier Inc. All rights are reserved, including those for text and data mining, AI training, and similar technologies.

A new test compression scheme is proposed by using a new DFT architecture, a new gating technique, and a new low-power test application scheme for circuits with a large number of unknown test response sources. A probabilistic measure is proposed to analyze the potential of scan flip-flops to capture unknown responses. All scan flip-flops with enough potential to capture unknown test responses are clustered to localize the effect of the unknown sources on fault coverage. A new test response compactor is presented to avoid unknown test responses and minimize fault coverage loss in the software-defined linear feedback shift-register (SLFSR) based test compression environment. Experimental results are presented to show the effectiveness of the new method.

Diagnosing faults in multiprocessor systems has long been significant due to its performance impact and its blend of Graph Theory and Computer Science concepts. In 2012, Peng et al. introduced the g-good-neighbor diagnosability, ensuring every fault-free node has at least g fault-free neighbors. This concept, gaining traction over the years, has led to extensive research on the connectivity and diagnosability of many prominent multiprocessor systems. In this paper, we introduce a novel comparison model, the MC model, for multiprocessor systems. This model integrates the strengths of both the PMC and MM⁎ models, optimizing computing power and time. We present an algorithm detailing the MC model's operations and establish the conditions for a multiprocessor system G to be g-good-neighbor t-diagnosable under the MC model. A general method to determine a G's g-good-neighbor diagnosability under the MC model is also provided. We further highlight the MC model's advantages over the PMC and MM (including MM⁎) models. Lastly, we apply the MC model to Hypercube, determining its g-good-neighbor diagnosability.

BCube stands as a renowned server-centric data center network (DCN), boasting numerous advantages, such as low diameter, high aggregate throughput, and abundant parallel paths. As DCNs expand rapidly, followed by the daily increasing likelihood of failures, fault tolerance has become an important issue in DCNs. Hamiltonian paths constitute a pivotal network topology for parallel and distributed computing, suitable for designing deadlock-free routing algorithms, fault-tolerant routing algorithms, and congestion avoidance. The partitioned edge fault (PEF) model is a recently proposed fault model that exploits the properties of networks to achieve fault tolerance with an exponential scale. In this paper, we explore the existence of Hamiltonian paths in BCube under the PEF model. Since one switch failure will result in multiple faulty links, we also extend the conclusions related to Hamiltonian paths to analyze the fault tolerance of BCube under the PEF model when switch failures occur. Moreover, we provide algorithms to embed a Hamiltonian path between arbitrary two distinct servers into BCube under the PEF model. Experimental analysis and comparisons demonstrate that our approach exhibits exponential enhancements over the other known results, and BCube DCNs possess remarkable fault tolerance in response to both link and switch failures under the PEF model. As a by-product, we obtain a deadlock-free routing based on the constructed Hamiltonian path and assess the routing performance compared to the benchmark routing algorithms.

Diagnosability is a fundamental consideration when designing an interconnected network. The PMC and MM* * fault diagnosis models are the two most commonly used models. Both the g-good-neighbour diagnosability and g-extra diagnosability of an interconnection network have been two of the hot topics in the intersectional research areas of Graph theory and Computer Science, which become increasingly attractive for new solutions to real-world problems. However, there are still some problems in the transformation from the concepts of Computer Science to that of mathematics. In this paper, we systematically study such problems and give a strict proof from concepts to mathematical conclusions. In the terms of results, we not only give the relationship between g-good-neighbour diagnosabilities of the network under PMC model and MM* * model, but also between g-extra diagnosabilities of the network under PMC and MM* * models. To apply our results, we give an application on the enhanced hypercube in the end and derive a lemma explaining whether these are 3-cycles in enhanced hypercubes and how many common neighbours for two vertices of enhanced hypercubes under different values of k in the meantime. (c) 2024 Elsevier B.V. All rights are reserved, including those for text and data mining, AI training, and similar technologies.

Logic built-in self-test and scan-based testability design are currently the mainstream solutions for large-scale integrated circuit testing. Phase shifters are widely used in these testing schemes because they can greatly improve the driving ability of test inputs and significantly improve the fault coverage of testing. A phase shifter is composed of an XOR network consisting of a certain number of multi-input XOR gates, and the correlation of the output sequence of the phase shifter has a significant impact on the testing performance. The classic constructing method of phase shifters has problems such as long running time, easy wiring conflicts during the actual synthesis and implementation of final circuits. Therefore, when encountering designs with large scanning units, they often face great difficulties. This article proposes a phase shifter constructing method based on grouping and random fan-in, which controls the register units that each scan chain excitation input depends on as much as possible within a local range, greatly reducing the computational time and wiring difficulty of phase shifter construction. At the same time, a linear feedback shift register bit with random fan-in is introduced to reduce the correlation between the output sequences of adjacent ports of the phase shifter. Using partial IWLS 2005 benchmark circuits and OpenCores test circuits, while ensuring the same test fault coverage for stuck-at faults and transition faults, this method reduces more than 30% running time to construct a phase shifter compared to classical methods. The phase shifter structures constructed for each test circuit are synthesized and implemented on Xilinx’s XC7V690T FPGA. The phase shifter constructed by this method consumes more than 20% less wiring resources than the phase shifter constructed by classical methods.

A new low-power test compression scheme, called Dcompress , is proposed for launch-on-capture transition fault testing by using a new seed encoding scheme, a new design for testability architecture, and a new low-power test application procedure. The new seed encoding scheme generates seeds for all tests by selecting a primitive polynomial that encodes all tests of a compact test set. A software-defined linear feedback shift register architecture, called SLFSR , is proposed to make the new method conform to the current flow of design and test. Experimental results on benchmark circuits show that test data volume can be compressed up to 6300X with the well-compacted baseline test set for a design with 11.8M gates and more than 1.1M scan flip-flops.

The Chiplet architecture has achieved great success in recent years. However, chiplet-based networks are significantly different from traditional networks, thus presenting new challenges in evaluation. On the one hand, on-chiplet and off-chiplet networks are tightly coupled; therefore, the entire heterogeneous network must be designed and evaluated jointly rather than separately. On the other hand, existing network simulators cannot efficiently evaluate large-scale chiplet-based networks with cycle-accurate accuracy. In this paper, we present the design and implementation of the Chiplet Network Simulator (CNSim), a cycle-accurate packet-parallel simulator supporting efficient simulation for large-scale chiplet-based (shared-memory) networks. In CNSim, a packet-centric simulation architecture and an atomic-based hyper-threading mechanism are adopted, accelerating simulation speed by 11 x 14 x compared with existing cycle-accurate simulators. Besides, we implement the heterogeneous router/link microarchitecture and many other features, including hierarchical topologies, adaptive routing, and real workload traces integration. Based on CNSim, two typical chiplet-based networks, which cannot be efficiently simulated by existing simulators, are systematically evaluated. The advantages and limitations of chiplet-based networks are revealed through systematical cycle-accurate simulations. The simulator and evaluation framework are open-sourced to the community.

The chiplet architecture is one of the emerging methodologies and is believed to be scalable and economical. However, most current multi-chiplet systems are based on one uniform die-to-die interface, which severely limits flexibility. First, any interface has specific applicable workloads/scales/scenarios; therefore, chiplets with a uniform interface cannot be freely reused in different systems. Second, since modern computing systems must deal with complex and mixed tasks, the uniform interface does not cope well with flexible workloads, especially for large-scale systems. To deal with these inflexibilities, we propose the idea of Heterogeneous Interface (Hetero-IF), which allows chiplets to use two different interfaces (parallel IF and serial IF) at the same time. Hetero-IF can combine the advantages of different interfaces and cover up the disadvantages of each, thus improving flexibility and performance. However, adopting hetero-IF-based multi-chiplet interconnection systems still faces many challenges. The microarchitecture, scheduling, interconnection, and routing issues have not been discussed so far. In this paper, we put forward two typical hetero-IF implementations: Hetero-PHY and Hetero-Channel. Based on these two implementations, detailed usages and scheduling methods are discussed. We also present the interconnection methods for hetero-IF-based multi-chiplet systems and show how to apply deadlock-free routing algorithms. Extensive evaluations, including simulation and circuit verification, are made on these systems. The experiment results show that hetero-IF provides more flexible interconnection and scheduling possibilities to achieve better performance and energy metrics under various workloads.

A new low-power test compression scheme, called Dcompress, is proposed for launch-on-capture (LOC) transition fault testing by using a new seed encoding scheme, a new design for testability architecture, and a new low-power test application procedure. The new seed encoding scheme generates seeds for all tests by selecting a primitive polynomial that encodes all tests of a compact test set. A software-defined linear feedback shift register architecture, called SLFSR, is proposed to make the new method conform to the current flow of design and test. Experimental results on benchmark circuits show that test data volume can be compressed up to 6300X with the well-compacted baseline test set for a design with 11.8M gates and more than 1.1M scan flip-flops.

The Chiplet methodology can accelerate VLSI system development and provide better flexibility. However, it is not easy to build interconnection networks across multiple chiplets and maintain high-performance deadlock-free routing in systems of various hierarchical topologies. In particular, most on-chiplet networks are based on flat topologies such as 2D-mesh, which are inflexible and insufficient for large-scale multi-chiplet systems.To take full advantage of the multi-chiplet architecture and advanced packaging, we propose an interconnection method that can flexibly establish high-radix interconnection networks from typical 2D-mesh-NoC-based chiplets. A minus-first-based deadlock-free adaptive routing algorithm and a safe/unsafe flow control policy are introduced for these multi-chiplet interconnection networks. Additionally, a general approach network interleaving is used to balance the communication bandwidth within and between chiplets.We evaluate different architectures and traffic patterns on a cycle-accurate C++ simulator. Compared with traditional adaptive routing in 2D-mesh, our methodology can significantly improve network performance in various cases. The more chiplets there are, the more effective the method is. For 64 4×4-2D-mesh-based chiplets, The maximum injection rate increase is up to 2×, and the average latency reduction is up to 45%.

Interconnection networks fall into two different classes: (1) low-radix networks, and (2) high-radix networks. High-radix networks mainly include fat-tree networks, and dragonfly related networks. Dragonfly related networks include the 1D dragonfly networks, 2D Slingshot networks, dragonfly+ networks and others. The 1D dragonfly networks consist of completely connected router groups, where each pair of router groups has one or multiple global optical connection. Each pair of routers in the same router group has a single local connection. The Slingshot networks replace the router group with a flattened butterfly 2D connected group, where every two groups can be connected by one or multiple global connections. The dragonfly+ network is an enhanced 1D dragonfly network, where each router group contains two sub-groups of switches: one called leaf switches, and the other are spine switches. The spine switches are directly connected to the spine switches of the other router groups while the leaf switches are connected to the spine switches in the same group and the servers. The speaker presents efficient routing algorithms, network connection schemes, and collective communication operations in different high-radix networks.

Compared with two-stage object detection algorithms, one-stage algorithms provide a better trade-off between real-time performance and accuracy.However, these methods treat the intermediate features equally, which lacks the flexibility to emphasize meaningful information for classification and location.Besides, they ignore the interaction of contextual information from different scales, which is important for medium and small objects detection.To tackle these problems, we propose an image pyramid network based on dual attention mechanism (DAIPNet), which builds an image pyramid to enrich the spatial information while emphasizing multi-scale informative features based on dual attention mechanisms for onestage object detection.Our framework utilizes a pre-trained backbone as standard detection network, where the designed image pyramid network (IPN) is used as auxiliary network to provide complementary information.Here, the dual attention mechanism is composed of the adaptive feature fusion module (AFFM) and the progressive attention fusion module (PAFM).AFFM is designed to automatically pay attention to the feature maps with different importance from the backbone and auxiliary network, while PAFM is utilized to adaptively learn the channel attentive information in the context transfer process.Furthermore, in the IPN, we build an image pyramid to extract scale-wise features from downsampled images of different scales, where the features are further fused at different states to enrich scale-wise information and learn more comprehensive feature representations.Experimental results are shown on MS COCO dataset.Our proposed detector with a 300 × 300 input achieves superior performance of 32.6% mAP on the MS COCO test-dev compared with state-of-the-art methods.

With the emergence of a large number of multi-core systems, many 3D routing schemes have been developed for network-on-chips (NoCs) in order to obtain low overhead and high-performance. Nevertheless, it is difficult to possess these characteristics for contemporary 3D routing algorithms. This study presents a new routing algorithm for 3D stacked NoCs based on the repetitive turn concept. The authors propose the high-performance minimum pressure turn model (MPTM) routing algorithm that can be applied to a 3D case. Repetitive prohibited turns are spread in the row and column of the planes and vertical direction in the MPTM routing algorithm with no virtual channels. Besides, the MPTM routing algorithm has minimum routing pressure by exploring the whole 3D space. Considering network average latency and throughput, the results acquired show that the MPTM scheme improves performance over existing work.

In this paper, we propose a new 3D Network-on-Chip(NoC) routing algorithm for vertically connected 2D mesh topology. There are many metrics to comment an efficient routing algorithm including high performance and cost-effective. However, existing 3D routing algorithms are unable to meet all these needs. We extend the high-performance 2D repetitive turn model(RTM) to a 3D scenario by applying their rules in 2D in addition to the new rules with respect to vertical turns to this end. The routing algorithms based on the 3D repetitive turn model have repetitive prohibited turns across the horizontal row, horizontal column and vertical direction without virtual channels. The simulation results demonstrate that the new 3D repetitive turn model approach could achieve lower latency and throughput improvement as compared to previous approaches which requires no virtual channel under uniform and non-uniform traffic pattern.

The connectivity and diagnosability of a multiprocessor system and an interconnection network are two important research topics. The system and the network have an underlying topology, which is usually presented by a graph. As a topology structure of interconnection networks, the [Formula: see text]-dimensional leaf-sort graph [Formula: see text] has many good properties. In this paper, we prove that (a) [Formula: see text] is tightly [Formula: see text] super connected for odd [Formula: see text] and [Formula: see text], and tightly [Formula: see text] super connected for even [Formula: see text] and [Formula: see text]; (b) under the PMC model and MM[Formula: see text] model, the diagnosability [Formula: see text] for odd [Formula: see text] and [Formula: see text], and [Formula: see text] for even [Formula: see text] and [Formula: see text].

A new weighted pseudo-random test generator called wPRPG is proposed for low-power launch-on-capture (LOC) transition delay fault testing. The low-power weighted PRPG is implemented by assigning different weights on the test enable signals and applying a gating technique. The new low-power PRPG can achieve much higher transition delay fault coverage in LOC delay testing than the conventional test-per-scan PRPG.

Performance and power are two conflict requirements in a NoC. It is attractive to propose a low-power and high-performance routing scheme. A new low-power fully adaptive routing algorithm is proposed for virtual cut-through or wormhole switched networks-on-chip. The following new techniques are proposed: (1) multiple packets can be delivered across the same physical channel via different bypassing channels, (2) a low-power bypassing hop can include both x and y channels, (3) a new low-power routing selection function is defined for more power reduction, (4) a new limited-global control signaling scheme is proposed, (5) a new cycle-accurate system-level power estimation model is proposed, and (6) bypassing hops of any lengths and the normal hops in the original network can share the same virtual channels. Simulation results are presented to evaluate the performance and power by comparison with some previous methods.