As a key step in digital integrated circuit (IC) design, logic synthesis involves various logic optimization algorithms, where the quality of results (QoR) depends heavily on the optimization sequence used. Exploring the optimization space is challenging as the number of potential optimal permutations grows exponentially. Traditional methods rely on manual adjustments by experts, but are difficult to deal with complex and different circuits, leading to significant optimality gaps. Many automatic methods have been introduced, but they still face problems of low generalization and low efficiency. In this work, we propose ORL-LO, a two-stage learning framework that leverages an offline reinforcement learning (RL) method (i.e., advantage-weighted actor-critic, AWAC) to pretrain on expert trajectories and finetune on target test circuits, enabling efficient exploration of optimal synthesis flows. Firstly, ORL-LO uses AWAC to pretrain a fast and high-performance intelligent policy to fully leverage the offline knowledge of a large corpus of high-quality expert trajectories. Then, the pretrained policy is finetuned for target circuits using AWAC and policy distillation to obtain better results. Compared with the state-of-the-art (SOTA) methods, our framework can effectively improve the quality of logic optimization and significantly speed up the exploration time.
Accurate parameter extraction for RF passive devices is a critical step in semiconductor design because compact models directly determine the reliability of circuit simulation. Conventional extraction remains highly iterative and depends on substantial expert intervention for parameter grouping, optimizer selection, range adjustment, and curve-quality assessment. This article presents ModelAuflow, a highly scaffolded LLM-orchestrated framework for RF passive-device parameter extraction. The framework combines structured LLM reasoning with deterministic strategy conversion so that high-level optimization decisions are mapped into executable commands for commercial extraction tools. To improve convergence efficiency, the system integrates sensitivity-aware parameter filtering, historical self-reflection, and a classification knowledge base. Across the evaluated RF passive-device cases, the framework reduced the RMSE of a complex inductor below 3.5%, a capacitor below 2%, and a resistor below 1%. Under favorable initial conditions, the shortest successful extraction required 134 seconds and one optimization attempt. These results indicate that schema-constrained LLM orchestration can substantially reduce continuous manual intervention while maintaining accurate extraction for the evaluated RF passive-device workflows.
Network-on-Chip (NoC)-based Multi-Processor Systems-on-Chip (MPSoCs) are increasingly required to execute multiple real-time applications simultaneously. Each application is modelled as a Directed Acyclic Graph (DAG) of dependent tasks, and the platform supports Dynamic Voltage and Frequency Scaling (DVFS). While existing task-mapping methods address energy efficiency, reliability, and network contention for a single DAG, they do not capture the inter-DAG contention that arises when communication flows from independent applications compete for shared NoC links, nor the cross-DAG resource sharing that forces tasks from different applications to be serialised on the same Processing Element (PE). In this paper, we formulate the multi-DAG contention- and reliability-aware task mapping problem as a Mixed-Integer Nonlinear Program (MINLP). To handle the quartic constraint growth that renders exact solvers impractical for realistic workloads, we propose MERC , a polynomial-time heuristic for the multi-DAG setting. MERC performs (i) global task placement with cross-DAG load balancing and (ii) joint V/F selection and edge scheduling via greedy list scheduling with worst-case contention slack, optionally followed by a contention refinement phase that computes precise inter-DAG slack and exploits recovered time for frequency reduction. Extensive simulations on random DAGs over 2 × 2 to 6 × 6 mesh topologies demonstrate that MERC provides the best multi-objective balance among all compared methods: 60% lower energy than round-robin placement, 10– \(56\% \) lower energy than an adapted multi-DTG heuristic (SAFLA-N), robust feasibility where independent single-DAG scheduling collapses at scale, and polynomial-time execution that is two orders of magnitude faster than a metaheuristic baseline. A cycle-accurate Noxim cross-check supports the reserved-path delay model under concurrent DAG traffic, and a case study of three edge applications confirms the same multi-objective reading.
Field-Coupled Nanocomputing (FCN) devices are emerging nanotechnologies for next-generation logic computing, driven by the physical limitations of CMOS technology. As the scale of circuit design increases, automatic placement and routing (P&R) become crucial for optimizing device performance and ensuring scalable fabrication. Previous algorithms face challenges in solving large-scale placement and routing problems with the current clocking scheme. In this article, a novel approach is proposed to decouple the placement and routing issues in the design of FCN logic circuits. By adopting a layered method, the issues are confined within each layer, and long wires between layers are eliminated while reducing crossovers through node sorting. A* algorithm is employed to solve the routing between logic gates, and an innovative clock allocation mechanism ensures clock synchronization. A standard cell library is used to implement the mapping of an FCN circuit from a gate-level layout to a nanocell-level layout. The proposed method demonstrates superior performance compared with state-of-the-art approaches such as fiction, Ropper, and genetic algorithms (GA). Specifically, it achieves higher success rates, fewer gates and faster execution times, along with lower delays–while also delivering reduced area overhead, particularly when compared with Ropper and GA. Furthermore, this article achieves automatic placement and routing of FCN circuits with over 1000 nodes, making it more suitable for large-scale FCN circuit design.
Recently, hybrid-row-height designs have been introduced to achieve performance and area co-optimization in advanced nodes. Hybrid-row-height designs pose significant layout/placement challenges due to the heterogeneous cell and row structures. In this article, we present an effective framework to address the hybrid-row-height placement problem in three major stages: (1) global placement, (2) legalization, and (3) detailed placement. Inspired by the multi-channel processing method in convolutional neural networks (CNNs), we use the feature extraction technique to equivalently transform the hybrid-row-height global placement problem into two sub-problems that can be solved effectively. We propose a multi-layer nonlinear framework with alignment guidance and a self-adaptive parameter adjustment scheme, which can obtain a high-quality solution to the hybrid-row-height global placement problem. In the legalization stage, we formulate the hybrid-row-height legalization problem as a convex quadratic programming (QP) problem, then apply the robust modulus-based matrix splitting iteration method (RMMSIM) to solve the QP efficiently. After RMMSIM-based global legalization, Tetris-like allocation is used to resolve remaining physical violations. In the detailed placement stage, we develop a whitespace-clustered cell reordering method and feature-aware cell matching method for wirelength optimization, then congestion-aware cell sliding is used to alleviate placement congestion. Compared with the state-of-the-art work, experiments on the 2015 ISPD Contest benchmarks show that our framework can achieve a 7% reduction in final total wirelength and 2.23× speedup.
