Operating Tensor Processing Units (TPUs) in the near-threshold computing (NTC) region significantly reduces energy consumption but introduces high delay sensitivity to process variation and data activity. Conventional designs typically rely on a conservative, fixed global clock to ensure safety, which leaves large portions of timing margin unexploited as most operations finish well before the clock edge. We propose Dynamic Slack-Aware Clocking (DSAC), a proactive framework that replaces worst-case timing with operation-specific adjustments. DSAC employs lightweight Hamming-Distance, Most-Significant-Bit, and Hybrid predictors to estimate the delay sensitivity of individual multiply-accumulate (MAC) operations and classify them into three timing tiers. These tiers are enforced locally via dummy-hold cycles under a fixed global reference clock, enabling fine-grained timing adaptation without global clock retuning or frequency scaling. A closed-loop feedback controller monitors timing violations and updates tier thresholds at runtime to maintain resilience. Experiments on quantized DNN benchmarks demonstrate that the MSB predictor maintains high inference accuracy, with an average loss of only 1% even at aggressive performance points. Furthermore, DSAC achieves up to 1.55 × better energy efficiency at 2.15 × frequency scaling compared to a baseline TPU, while incurring an area overhead as low as 13%.
Approximate computing exploits the inherent error tolerance of many applications to achieve significant improvements in area, energy, and performance. This work proposes a novel method to determine the smallest possible hardware design that satisfies a given maximum error threshold ( E max ) using High-Level Synthesis (HLS). HLS tools rely heavily on synthesis directives (pragmas) to control how arrays (e.g., RAMs, ROMs, registers), functions (e.g., inline, goto), and loops (e.g., full unroll, partial unroll, pipeline) are implemented. In this work we leverage this and introduce an automated, approximation-aware HLS design space exploration framework guided by an Approximation Friendliness Index (AFI), a static metric that can be computed efficiently. This index enables the rapid identification of hardware implementations generated by setting unique HLS pragma combinations, with high potential for approximation, allowing the proposed framework to approximate only the most promising designs rather than every variant generated during the exploration process. Finally, recognizing that many hardware systems are organized as dataflow architectures, where multiple components are connected sequentially (e.g., JPEG), we extend our approach to optimize the entire dataflows given as separated individual behavioral descriptions for HLS. The proposed method identifies the best pragma combinations and set of approximations in each description to minimize the overall design size while maintaining accuracy at the primary outputs of the dataflow within E max . Experimental results show that this approach leads to basically the same results as exhaustively approximating every new design, while being substantially faster.
Hardware verification of the register transfer level (RTL) designs is a critical step in the development of complex digital circuits, ensuring their functional correctness, performance, and reliability. Within this crucial process, bug localization is an essential component for precisely identifying the root causes of design errors. Dynamic bug localization (DBL) stands out as an efficient and automatic approach to locate bug source code by calculating statement suspiciousness based on execution traces. However, DBL methods rely solely on coverage information and simplistic statistical formulas to compute suspiciousness, which has been criticized for their limited precision and inadequate reduction of debugging effort. In this paper, we propose MulFetFL: a multi-features deep learning based bug localization for RTL designs. MulFetFL begins by extracting three multimodal features: abstract syntax tree (AST) features, signal features, and timing features from designs. It then employs Graph Attention Networks (GAT) to enhance node representations. A cross-modal attention mechanism is subsequently applied to fuse these complementary features from different modalities. Finally, the fused features are passed through a multi-layer perceptron (MLP) to compute the suspiciousness score for each statement. Experimental results show that MulFetFL effectively locates 293, 295 and 298 bugs within Top-1/Top-3/Top-5 ranks, significantly outperforming state-of-the-art bug localization methods across a range of benchmark designs.
Today’s large-scale designs leverage power gating to achieve low power consumption, which necessitates the design of an efficient power switch network that accounts for both inrush current and wakeup latency. Optimizing this power switch network involves striking a balance between minimizing inrush current and reducing wakeup latency. However, analyzing inrush and wakeup latency for a given network is computationally expensive, particularly for complex systems, making optimization frameworks that rely on analysis engines prohibitively slow. To address this challenge, we frame the analysis of inrush and wakeup latency as a regression problem and train machine-learning (ML) models to predict these metrics. The ML model achieves mean errors of less than 10% for inrush current prediction and for wakeup latency prediction, while providing a speedup of over 50× compared to SPICE. By leveraging an ML model, we efficiently explore the design space and identify optimized power switch network patterns that minimize both wakeup latency and inrush current.
As FPGA design complexity increases, the correctness and reliability of logic synthesis tools are critical to ensuring correct hardware implementation. These tools translate hardware description languages (e.g., Verilog) into gate-level netlists, where latent faults may introduce functional errors or performance degradation during synthesis. Existing approaches rely on automatically generated Verilog test cases to find these latent faults. However, their effectiveness depends heavily on generator configurations and is typically guided by input diversity, which fails to accurately capture differences in synthesis behavior. Moreover, the high-dimensional configuration space of generator further hinders efficient exploration. To address these challenges, we propose SynaSpace, a behavior-driven configuration optimization framework for fault detection in logic synthesis tools. SynaSpace focuses on synthesis behavior coverage to guide configuration search, by constructing behavioral representations through joint analysis of synthesis logs and gate-level netlists. The framework comprises four components: (1) configuration space modeling for unified parameter representation; (2) Bayesian optimization–based configuration search for efficient exploration; (3) synthesis behavior characterization and coverage evaluation for capturing and quantifying behavioral differences; and (4) fault detection and utility modeling for extracting effective feedback via differential testing and deduplication. These components are integrated into a unified optimization framework to enable efficient configuration exploration and improved testing effectiveness. We evaluate SynaSpace on two established logic synthesis tools (i.e., Vivado and Yosys). SynaSpace identifies 18 faults across four categories, all of which have been confirmed and fixed by vendors and the open-source community.
AI workloads increasingly demand high parallelism and efficient on-chip memory utilization on modern GPUs. However, the limited capacity of shared memory often constrains thread-level parallelism, while portions of the L2 cache remain underutilized. In this work, we propose SAI , a mechanism that virtualizes shared memory into the L2 cache to improve GPU performance for AI applications. SAI dynamically activates virtualization based on runtime resource usage, enabling additional CTAs with minimal architectural modifications. We further introduce an L2 cache management strategy that integrates associativity-based virtual page allocation and a replacement information table, reducing page-swapping overhead while preserving L2 cache performance. Experimental results demonstrate that SAI achieves an 18.6% performance improvement over the baseline design and outperforms SMILE-opt, our reproduced state-of-the-art baseline, by 8.8%. Moreover, SAI captures 60.2% of the performance gain delivered by the idealized Double SMEM design while reducing energy consumption to 87.7% of the baseline. These results highlight the effectiveness of SAI in enhancing thread-level parallelism and optimizing on-chip memory for AI workloads.
Quantum computing has the potential to accelerate various fields by solving specific problems significantly faster than classical computers. Solving more complex problems generally requires a larger number of qubits. However, current quantum devices are constrained by limited qubit counts and environmental noise. Quantum circuit cutting bridges the gap between the theoretical requirements of large quantum circuits and the practical limitations of current quantum hardware by decomposing large circuits into smaller subcircuits. Tang et al. introduced CutQC, a framework that reduces the number of generated subcircuits and reconstructs the complete quantum state with limited memory consumption. Despite these advances, CutQC faces performance bottlenecks in classical postprocessing, leading to long execution times. To address this limitation, we propose QCutSim, an efficient simulation-based framework guided by insights from the postprocessing stage. It improves performance through optimized simulation and reconstruction strategies, along with computational optimizations such as vectorization and parallelization. QCutSim demonstrates that even consumer-grade systems can efficiently simulate 100-qubit circuits and achieves a speedup of up to 5.1x compared to prior work on the same hardware. In the worst-case scenario of reconstructing dense solution circuits, QCutSim achieves a speedup of 6 to 8 orders of magnitude.
In a chiplet-based design, logic blocks (chiplets) are connected by a large number of interconnects to form larger functions. The interconnects require comprehensive testing to ensure that the design operates correctly. The interconnects are tested using isolation logic to support comprehensive structural testing. It was also suggested to test the interconnects together with the logic block that drives them in a closer to functional mode of operation. In this approach, fault effects are captured at the destination of the interconnects. Whereas the isolation logic on the source of the interconnects is bypassed, the isolation logic on their destination is not. This article suggests for the first time an approach where the isolation logic on both the source and destination of the interconnects is bypassed, operating the same as during functional operation. This requires an interconnect fault model that specifies fault effects. In addition, sequential test generation is used for more complete testing under functional operation conditions. Sequential test generation is applied only to interconnect faults to limit the computational effort. To further limit the computational effort, the article introduces a notion of potentially undetectable interconnect faults that is specific to this model. Experimental results for benchmark circuits in an academic simulation environment demonstrate the effectiveness of sequential test generation in this context.
With the continued advancement of Very Large-Scale Integration (VLSI) technology, IR drop in Power Delivery Networks (PDNs) poses a serious threat to chip performance and reliability. Due to the complex cross-scale interactions between local hotspots and global power paths in real-world scenarios, existing approaches face the challenges of lacking a coupled representation of multi-scale features and ignoring long-range dependencies and spatiotemporal feature fusion. This severely limits the ability of IR drop prediction approaches to capture voltage-drop hotspots, undermining the accuracy and reliability of their predictions. Therefore, this paper proposes a novel prediction framework named IR-Hunter. IR-Hunter first employs heterogeneous convolution kernels to model local electrothermal hotspots and global PDN impedance distributions, precisely capturing hotspot locations and macro-scale current-flow paths critical for chip layout and routing. Then, it adaptively fuses these multi-scale features. Additionally, IR-Hunter learns global power interactions within the PDN to identify long-range voltage coupling effects affecting routing and power-grid stability. Finally, IR-Hunter leverages cross-metal-layer current propagation pathways, efficiently integrating cross-scale spatiotemporal information between the encoder and decoder stages, consistently improving IR drop prediction accuracy during chip design. Comprehensive experiments conducted on 20,578 samples collected from over 20K instances demonstrate IR-Hunter’s superior prediction accuracy, achieving an average 4.57% NRMSE reduction and 4.12% SSIM improvement compared to state-of-the-art approaches. Additionally, to foster advancements in the EDA community, we have open-sourced the code at https://github.com/xhhlzy/IR-Hunter.
The shift towards decentralized microelectronics manufacturing creates significant security vulnerabilities. Untrusted partners, foundries, and testing facilities gain full design access, enabling them to inspect, reverse engineer, and compromise critical security features. Sophisticated design-for-security (DfS) primitives have been developed to counter these threats; however, this article demonstrates that these primitives can be systematically dismantled by hardware Trojans (HT), which represent the ultimate insider threat within untrusted ecosystems. We introduce the concept of Trojan-assisted meta-attacks; a new attack paradigm in which Trojans structurally neutralize protections rather than algorithmically bypassing them. Adversaries leverage comprehensive design knowledge from supply chain access, employing advanced netlist analysis and data-flow examination to precisely identify and subvert security infrastructure. We present a unified meta-attack framework that generalizes across DfS primitives, supported by case studies on Physically Unclonable Functions (PUFs) and Dynamically Obfuscated Scan Chains (DOSC). Our systematic methodology achieves highly accurate security primitive identification through heuristic algorithms and machine learning approaches. Case studies demonstrate a complete authentication bypass through the extraction of PUF challenge–response pairs and an attack that disables DOSC protections by exploiting its deterministic structure. Together, these results show that meta-attacks constitute a broader paradigm shift in hardware security, exposing vulnerabilities across diverse DfS primitives. To address this challenge, we evaluate countermeasures that provide significant security improvements with reasonable overhead. By framing both the attacks and defenses within a unified meta-attack/defense framework, this work establishes a foundation for future research on Trojan-aware security architectures and underscores the urgent need to design protections that remain effective even under structural compromise.
Clock gating reduces dynamic power by integrating activation functions and integrated clock gating (ICG) cells into the clock path, selectively disabling the clock signal to register when unnecessary. While conventional activation function extraction methods rely on manual design or register-transfer level analysis, a gate-level alternative exists: deriving activation functions through the extraction of observability don’t care (ODC) conditions from the underlying netlist. This paper presents ODCGate , a framework designed to automatically detect ODC conditions as the activation functions and safely block clock transitions for unused registers, thereby further reducing dynamic power consumption during clock gating. The computation begins with cut boundary enumeration and simulation. To further minimize additional PPA overhead, we apply hybrid simplification techniques to the extracted logic, and enable sharing among registers through clustering. Experimental results show that, beyond the clock gating optimization of a commercial logic synthesis tool, our method achieves an average 33.46% additional reduction in dynamic power, with minimal impact on other PPA metrics.
Chip aging results in defects that are initially likely to appear as small delay defects. Path delay faults are used for detecting small delay defects. Because of the number of paths, path selection procedures are used for identifying a subset of path delay faults that are important to detect. A recent path selection procedure addresses small delay defects that are likely to occur because of chip aging. The procedure identifies a set of functionally possible path delay faults, from which it selects a subset based on an aging aware metric. This article studies this problem when the requirement for the path delay faults to be functionally possible is removed. The problem becomes that of selecting path delay faults through the largest numbers of transition faults with the highest susceptibilities to aging, and performing test generation for the selected path delay faults. Experimental results of path selection and test generation for benchmark circuits demonstrate the effectiveness of the procedures, and the differences from the case where the path delay faults are required to be functionally possible.
Logic locking is an integrated circuit (IC) encryption technique that incorporates key gates and key inputs into a circuit, ensuring correct functionality only when the correct key is applied. Traditional logic locking techniques are vulnerable to the satisfiability (SAT)-based attack method, also known as SAT attack, which decrypts circuits by quickly isolating incorrect keys. Consequently, recent methods employ one-point functions, such as AND-trees, in encrypted circuits to ensure that only one incorrect key is pruned per SAT attack iteration, thereby slowing decryption exponentially. However, these defense methods result in minimal output corruption. Subsequently, solutions like CAS-Lock have emerged, designed to enhance SAT attack resilience and maintain high output corruption, but they remain susceptible to structural attacks. In this work, we introduce the Big+little trees encryption framework to improve output corruption and strengthen resilience against SAT attacks, while effectively concealing structural vulnerabilities to prevent structural attacks. Experimental results show that our method maintains resilience against SAT, Valkyrie, KRATT and FALL attacks while ensuring significant output corruption.
Electronic Design Automation (EDA) tool chain plays a critical role in the design and manufacturing of Printed Circuit Boards (PCBs). Defects in the EDA tool chain can introduce errors into Printed Circuit Board (PCB) designs and manufacturing processes, potentially leading to system failures in these applications. Therefore, verifying the reliability of the EDA tool chain is crucial. In recent years, various approaches have been proposed based on automatically generated circuits to detect defects in the EDA tool chain. However, differential testing is often bottlenecked by two practical limitations of existing circuit schematic generators: limited coverage of structurally expressive and behaviorally diverse schematics, and the lack of functionally matched variants for controlled comparison, which reduces its effectiveness in exposing subtle defects in the EDA tool chain. Addressing these challenges, we present a circuit generator (Cir-Fuzzer) for automatically generating structurally and functionally diverse circuits, as well as functionally equivalent yet structurally varied circuit variants, to detect defects in the EDA tool chain. Specifically, Cir-Fuzzer consists of three components: diversity-enhanced synthesis and optimization component constructs structurally diverse and functionally valid circuits by applying pin-level constraints and eliminating redundant paths, facilitating the generation of realistic and effective test cases for exposing tool chain weaknesses; Functionally Equivalent Circuit (FEC) variant generator introduces slight perturbations into the original schematics without compromising circuit functionality, thereby expanding the circuit transformation space and enhancing the Cir-Fuzzer’s capability to uncover latent defects in the EDA tool chain; differential testing component leverages netlists generated from original circuits and their variants to compare simulation results across simulators, versions, and circuit variants, enabling the detection of inconsistencies and the revelation of hidden defects within the EDA tool chain. Experimental results demonstrate that Cir-Fuzzer outperforms baseline approaches in detecting more tool chain defects and has uncovered 12 real defects, 4 of which were officially confirmed or fixed by vendors.
This paper describes a system for modeling nonidealities in a silicon-photonic joint transform correlator (JTC) used as an accelerator for convolutional neural networks (CNNs). The system is used to determine which nonidealities have the greatest impact on end-to-end model accuracy, which helps determine what design choices can be made at the block and system level to improve performance. We create a digital twin of the on-chip 1D JTC using transfer functions fitted from simulations, then introduce a scalar α that mixes ideal and realized behaviors. We quantify the α -dependent model accuracy on CIFAR-10 and SNDR differences at both the joint-power spectrum (JPS) and the JTC output. The framework allows quantification of block- and system-level sensitivities, informing design choices by isolating the accuracy bottlenecks within the system.
Ising machines offer a promising paradigm for solving NP-hard combinatorial optimization problems (COPs). Among various approaches, Compute-in-Memory (CIM) based Ising machines show superior performance due to the reduced data transfer and efficient Multiply-and-Accumulate (MAC) operation. However, the scalability of CIM-based implementations remains limited due to challenges including restricted mapping size, circuit limitations and device non-idealities especially with emerging non-volatile memory (eNVM) technologies. This work presents a comprehensive design space exploration of three scalable CIM architectures for fully connected Ising models, analyzing their performance under constraints such as IR-drop, device variation, parasitic capacitance and analog to digital converter (ADC) precision loss across different memory technologies. According to our evaluation for randomized MAX-CUT benchmarks, the properly chosen design (Single array XNOR-based CIM mapping with Current Sense Amplifier) maintained over 95% solution quality while achieving nearly 2 × higher energy efficiency and a 40% area reduction for 128-spins Ising model, while the optimal solution (Distributed subarray computation with 1-bit ADC precision loss) improves energy efficiency by 2.1 × with small solution quality degradation ( \(\sim 10\% \) ) for large-scale models (1024 spins) compared to other designs options.
To address the growing computational demands of high-performance computing (HPC) and machine learning (ML) applications, Graphics Processing Units (GPUs) have transitioned from single-chip designs to multi-chip module (MCM) architectures, driven by manufacturing constraints. Simultaneously, GPUs are increasingly deployed in cloud environments to accelerate a wide range of applications for multiple users. Spatial multitasking, which allows multiple applications to run concurrently on a single GPU by executing them on different sets of streaming multiprocessors (SMs), offers an efficient method for sharing GPU resources. However, effectively supporting multitasking in the emerging MCM-GPU architecture presents a significant challenge that remains an open problem. This paper presents the key observation that the placement of co-executing applications in MCM-GPUs plays a critical role in system performance. Specifically, for certain multiprogram workloads, co-executing applications achieve better performance when located on the same GPU chip to maximize memory bandwidth utilization. Conversely, other workloads benefit from being distributed across different GPU chips to mitigate memory contention. To address this, we propose a Location-Aware Scheduler (LA-Scheduler) that identifies application characteristics and makes optimized scheduling decisions. The LA-Scheduler performs lightweight workload classification using a k-means-based clustering method and applies multitasking scheduling rules during runtime to determine the optimal placement of applications within the MCM-GPU architecture. Evaluation results show that the proposed LA-Scheduler improves system throughput (STP) by an average of 38.67% compared to single-task operation. Compared to the traditional methods intra-chip scheduling and inter-chip scheduling, the system throughput is improved by an average of 13.51% and 7.14% respectively.
Early access to accurate congestion information can effectively optimize the physical design flow of modern very large scale integration (VLSI) circuits. Existing unimodal models suffer from limited feature utilization and insufficient prediction accuracy, while current multimodal approaches typically involve large parameter sizes, slow inference, and high computational complexity, making them difficult to apply in time-critical tasks. To address these limitations, we propose CGNet, a novel lightweight multimodal model for congestion prediction that simultaneously processes feature maps and heterogeneous graphs. To enable efficient feature fusion without significantly increasing model complexity, we incorporate a cross-stitch module. Furthermore, we propose a heterogeneous graph compression method that significantly simplifies the graph structure, thereby reducing the computational complexity of processing heterogeneous graphs and improving the prediction speed of the model. Additionally, we design a composite loss function that jointly captures global structures and local details. For a more comprehensive evaluation, we propose a localized metric, intersection over union (IOU), and integrate the predicted congestion maps into the downstream design rule check (DRC) violation prediction task. Experimental results in the CircuitNet-N28 dataset demonstrate that CGNet consistently outperforms the best-performing model in both prediction accuracy and prediction speed.
Timing models in conventional technology libraries assume that only one input pin switches during a transition, while all side inputs are held to constant values. This assumption neglects the significant impact of multiple-input switching (MIS), which becomes increasingly relevant at advanced process nodes due to higher clock frequencies. The MIS can lead to two critical problems: delay variations and glitches at the output pin. In this article, we focus on addressing the problem of MIS-induced glitches, and to tackle this challenge, we propose an artificial neural network (ANN)-based model to predict the characteristics of these glitches. We demonstrate that the characteristics of glitches, such as their height and area, depend on the capacitive load, transition time at the inputs, and the temporal distance between signals at the inputs. Subsequently, we develop a methodology to generate and optimize a comprehensive dataset using these features, which is then utilized to develop the proposed model, minimizing computational costs while ensuring thorough glitch characterization. To minimize the number of SPICE simulations required for generating training datasets of complex logic gates, we formulate the identification of glitch-prone MIS transitions as a satisfiability (SAT) problem and employ a SAT solver to efficiently prune the search space. Using an ISCAS benchmark circuit, we demonstrate that these predictions from the proposed model are reasonably accurate (average RRMSE 3.44% and maximum RRMSE of 5.51% compared to reference SPICE simulations). Also, the proposed model offers ∼ 10,000 × times improvement during inference over conventional SPICE computations. The existing timing libraries augmented with the proposed model thus can be utilized in design optimization. We also illustrate the use of the proposed model in glitch attenuation algorithms for design transformations’ evaluation. Furthermore, the signal integrity and noise analysis tools can also employ the proposed glitch prediction model, as demonstrated in this article.
As semiconductor manufacturing advances toward smaller process nodes and more complex layouts, lithography hotspot detection faces increasing challenges. Traditional methods often struggle to capture subtle geometric variations in complex layouts, resulting in low recall and high false alarm rates. To address this problem, we propose a Multi-Scale Feature Refinement Network. The key innovation lies in a collaborative “Extraction–Refinement–Decision” framework specifically designed for Hard-To-Classify samples: the Multi-Scale Feature Extraction module comprehensively captures rich information ranging from local geometric details to global layout context; the Feature Refinement Network enhances responses to critical geometric features through a lightweight gating mechanism; and finally, ConvNeXt serves as the decision module, integrating and classifying the refined features for final hotspot prediction. Experimental results show that on the most challenging ICCAD 2019-2 benchmark, MSFRN improves recall by up to 11.3%, with the false alarm rate varying from a 0.2% increase to a 5.8% reduction, demonstrating superior detection capability.
