An N-bit priority resolver having N inputs and N outputs functions as polling hardware in an embedded system, enabling access to a resource when multiple devices initiate access requests at its inputs which may be located on-chip or off-chip. Subsystems such as data buses, comparators, fixed- and floating-point arithmetic units, interconnection network routers, etc., utilize the priority resolver function. In the literature, there are many transistor-level designs for the priority resolver based on dynamic CMOS logic, some of which are modular and others are not. This article presents a novel gate-level modular design of priority resolvers that can accommodate any number of inputs and outputs. Based on our modular design architecture, small-size priority resolvers can be conveniently combined to form medium- or large-size priority resolvers along with extra logic. The proposed modular design approach helps to reduce the coding complexity compared to the conventional direct design approach and facilitates scalability. We discuss the gate-level implementation of 4-, 8-, 16-, 32-, 64-, and 128-bit priority resolvers based on the direct and modular approaches and provide a performance comparison between these based on the design metrics. According to the modular approach, different sizes of priority resolver modules were used to implement larger-size priority resolvers. For example, a 4-bit priority resolver module was used to implement 8-, 16-, 32-, 64-, and 128-bit priority resolvers in a modular fashion. We used a 28 nm CMOS standard digital cell library and Synopsys EDA tools to synthesize the priority resolvers. The estimated design metrics show that the modular approach tends to facilitate increasing reductions in delay and power-delay product (PDP) compared to the direct approach, especially as the size of the priority resolver increases. For example, a 32-bit modular priority resolver utilizing 16-bit priority resolver modules had a 39.4% reduced delay and a 23.1% reduced PDP compared to a directly implemented 32-bit priority resolver, and a 128-bit modular priority resolver utilizing 16-bit priority resolver modules had a 71.8% reduced delay and a 61.4% reduced PDP compared to a directly implemented 128-bit priority resolver.

We present a new carry look-ahead adder (NCLA) architecture that makes use of non-uniform-size CLA modules in contrast to the existing CLA architecture which typically makes use of uniform-size CLA modules. This helps to achieve improved speed and energy efficiency for the NCLA architecture compared to the existing CLA architecture without incurring notable area and power penalties. To demonstrate the advantage of NCLA, several adders were implemented ranging from the slow ripple carry adder to the generally considered fastest parallel-prefix adder viz. the Kogge-Stone adder (KSA), and their performance metrics were compared. The 32-bit addition was considered an example, and the different adders were implemented in a semi-custom design method using a 28-nm CMOS standard digital cell library. Based on the synthesis results, the NCLA was found to facilitate significant optimizations in design metrics compared to its high-speed counterparts. To give some examples, the NCLA achieved: (i) a 14.7% reduction in delay and a 13.4% reduction in energy compared to a high-speed CLA while occupying slightly more area, (ii) a 42.1% reduction in delay and a 58.3% reduction in energy compared to a conditional sum adder while occupying 8% more area, (iii) a 14.7% reduction in delay and a 37.7% reduction in energy compared to a speed-optimized carry select adder while requiring 37% less area, and (iv) a 20.2% reduction in energy and a 55.4% reduction in area compared to the KSA.

We introduce a new carry look-ahead adder (NCLA) architecture that employs non-uniform-size carry look-ahead adder (CLA) modules, in contrast to the conventional CLA (CCLA) architecture, which utilizes uniform-size CLA modules. We adopted two strategies for the implementation of the NCLA. Our novel approach enables improved speed and energy efficiency for the NCLA architecture compared to the CCLA architecture without incurring significant area and power penalties. Various adders were implemented to demonstrate the advantages of NCLA, ranging from the slower ripple carry adder to the widely regarded fastest parallel-prefix adder viz. the Kogge–Stone adder, and their performance metrics were compared. The 32-bit addition was used as an example, with the adders implemented using a semi-custom design method and a 28 nm CMOS standard cell library. Synthesis results show that the NCLA architecture offers substantial improvements in design metrics compared to its high-speed counterparts. Specifically, an NCLA achieved (i) a 14.7% reduction in delay and a 13.4% reduction in energy compared to an optimized CCLA, while occupying slightly more area; (ii) a 42.1% reduction in delay and a 58.3% reduction in energy compared to a conditional sum adder, with an 8% increase in the area; (iii) a 14.7% reduction in delay and a 37.7% reduction in energy compared to an optimized carry select adder, while requiring 37% less area; and (iv) a 20.2% reduction in energy and a 55.4% reduction in area compared to the Kogge–Stone adder.

This article introduces a new fault-tolerant design approach based on approximate computing, called FAC, for designing redundant circuits and systems. Traditionally, triple modular redundancy (TMR) has been used to ensure complete tolerance to any single fault or a faulty processing unit, where the processing unit may be a circuit or a system. However, TMR incurs more than 200% overhead in terms of area and power compared to a single processing unit. Alternative redundancy approaches have been proposed in the literature to mitigate these overheads associated with TMR, but they provide only partial or moderate fault tolerance. Among the alternatives, majority voting-based reduced precision redundancy (MVRPR) may be useful for error-resilient applications such as digital signal processing. While MVRPR guarantees only moderate fault tolerance, the proposed FAC is well-suited for error-resilient applications and ensures 100% tolerance to any single fault or a faulty processing unit, like TMR. In this work, we evaluate the performance of TMR, MVRPR, and FAC for a digital image processing application. The image processing results obtained demonstrate the effectiveness of FAC. Moreover, when the processing unit is implemented using a 28-nm CMOS technology, FAC achieves significant improvements over TMR, including a 15.3% reduction in delay, a 19.5% reduction in area, and a 24.7% reduction in power. Compared to MVRPR, FAC exhibits notable enhancements, with an 18% reduction in delay, a 5.4% reduction in area, and an 11.2% reduction in power. When considering the power-delay product, which reflects energy efficiency, FAC demonstrates a 36.2% reduction compared to TMR and a 27.2% reduction compared to MVRPR. When considering the power-delay-area product, which represents design efficiency, FAC achieves a 48.7% reduction compared to TMR and a 31.1% reduction compared to MVRPR.

This paper presents a novel Fault-tolerant design i.e., redundancy strategy based on Approximate Computing, which we call FAC. Conventionally, triple modular redundancy (TMR) has been widely used to guarantee 100% tolerance to any single fault or failure of a processing unit where the processing unit may be a circuit or system. However, TMR results in more than 200% overhead in area and power compared to a single processing unit. To reduce the overheads in design metrics associated with TMR, alternative redundancy approaches were presented in the literature but they guarantee only partial or moderate fault tolerance. Nevertheless, among these alternative redundancy approaches, the majority voter-based reduced precision redundancy (MVRPR) may be useful for naturally error-resilient applications like digital signal processing which is commonly used in space systems. The proposed FAC is ideally suited for error-resilient applications but unlike MVRPR which guarantees only a moderate fault tolerance, FAC guarantees a 100% tolerance to any single fault or failure of a processing unit like TMR. We considered TMR, MVRPR, and FAC to comparatively evaluate their performance for a digital image processing application. The image processing results obtained demonstrate the usefulness of FAC. Further, for a physical implementation using a 28-nm CMOS technology, FAC achieves a 15.3% reduction in delay, 19.5% reduction in area, and a 24.7% reduction in power compared to TMR, and an 18% reduction in delay, 5.4% reduction in area, and 11.2% reduction in power compared to MVRPR.

Given the continuing miniaturization of underlying transistors, electronic functional units (circuits/systems) become increasingly susceptible to high-energy radiation, encountered in applications like space. Hence, redundancy is employed as a radiation hardening by design strategy to cope with faults of functional units used in such applications and to maintain their correct operation. Triple modular redundancy (TMR), which is a subset of N-modular redundancy (NMR), that can mask any single fault or a faulty functional unit has been widely used. However, compared to a simplex implementation a TMR implementation requires two additional functional units and a majority voting logic therefore a TMR implementation's area and power overheads are greater by over 200 %. This is burdensome for resource-constrained applications like space where low power and energy efficiency are important considerations. This paper presents a new redundancy strategy involving approximate computing called RESAC for error-tolerant applications such as digital image/video/audio processing, which is used in space systems. We evaluated the feasibility of RESAC for an image processing case study and the results confirm the usefulness. For implementation using a 28-nm CMOS technology, RESAC achieves reductions in area, delay, and power by 22.3 %, 15.3 %, and 24.9 % compared to TMR. Nonetheless, RESAC can address any NMR.

This article presents a novel approximate adder that is design-optimized and has optimized error metrics. Optimization in design translates into optimization of the design parameters such as delay, power, and area/resources, and optimization of the error metrics points to the usefulness of the proposed approximate adder for practical applications. We refer to the proposed approximate adder that is hardware optimized and having a near-normal error distribution as HOAANED, in short. We consider the implementation of HOAANED and the other approximate adders based on ASIC and FPGA design environments. We used a Xilinx Artix-7 device for a FPGA implementation, and a 32/28-nm CMOS standard digital cell library for an ASIC based implementation. To demonstrate the practical utility of HOAANED, we considered digital image processing as a practical application and performed experimentation with many images. The quality of the images reconstructed using the approximate adders was analyzed based on the peak signal-to-noise ratio (PSNR), which is used as a qualitative figure-of-merit to assess the images. It is found that HOAANED achieves an improved PSNR in comparison with the other approximate adders for image processing, and this is achieved with HOAANED simultaneously featuring optimized design metrics and error characteristics.

This paper investigates the application of approximate addition in digital image compression. Discrete cosine transform (DCT) is an important operation in digital image compression and we considered utilizing accurate addition and approximate addition separately while calculating the DCT. Accurate addition was performed using the accurate adder and approximate addition was performed using different approximate adders. Accurate and approximate adders were implemented in an ASIC design environment using a 32-28nm CMOS standard cell library and in a FPGA design environment using a Xilinx Artix-7 device. Error analysis has been performed to calculate mean absolute error and root mean square error of approximate adders by considering one million random input vectors. It is observed that approximate adders help to better reduce the file size of compressed images than the accurate adder. Simultaneously, the approximate adders enable reductions in design metrics compared to the accurate adder. For a FPGA implementation, an optimum approximate adder achieves 8% delay reduction and 19.7% power reduction while consuming 47.6% fewer LUTs and 42.2% fewer flip-flops compared to the accurate FPGA adder. With respect to an ASIC based implementation using standard library cells, an optimum approximate adder achieves 27.1% delay reduction, 46.4% area reduction and 50.3% power reduction compared to a high-speed accurate carry look-ahead adder.

Image blending, which involves a mix of images, is used in computer graphics and photo editing. For example, two images can be blended through addition or multiplication. Usually, accurate addition or multiplication is performed to blend the images. In this paper, we discuss image blending using approximate multiplication. We show that approximate multiplication can yield visually similar blended images as accurate multiplication through an example illustration. We discuss a systematic approximation of the accurate array multiplier by introducing a series of vertical cuts in it and assign different combinations of binary values to the dangling internal inputs and dangling product bits. For an 8x8 image blending operation, our proposed approximate array multiplier is found to achieve 21 % reduction in delay, 63.3% reduction in area, and 72.3% reduction in power compared to the accurate array multiplier while yielding a visually acceptable blended image. Further, compared to a highspeed accurate multiplier that was directly synthesized using a logic synthesis tool, our proposed approximate array multiplier reports 9.7% reduction in delay, 60.6% reduction in area, and 64.7% less power. The multipliers were physically realized using a 32/28-nm CMOS technology.

We present a new approximate adder with reduced error and optimized design metrics. The proposed approximate adder is derived by modifying an existing approximate adder HERLOA and is called modified HERLOA or M-HERLOA in short. We considered a systematic modification of HERLOA to derive an optimum M-HERLOA for a digital image processing application. We calculated popular error parameters such as mean absolute error (also called mean error distance) and root mean square error of the approximate adders. We estimated the design metrics of accurate and approximate adders based on FPGA and ASIC (standard cell based) implementations. We compare the performance of accurate adder and approximate adders for an image processing application by estimating the peak signal to noise ratio and structural similarity index metric. We find that the proposed M-HERLOA reconstructs a digital image that is similar to the image reconstructed using the accurate adder. This is achieved with M-HERLOA simultaneously enabling following optimizations in design metrics compared to the accurate adder for a 32 bit addition: (i) 9.5% reduction in minimum clock period, 9.1% reduction in total on-chip power consumption, and 7 LUTs and 18 flip-flops less for a FPGA implementation, and (ii) 18% reduction in critical path delay, 26.7% reduction in average power dissipation, and 23.1% reduction in silicon area for an ASIC type implementation.

Authors make a change because the modification is required to ensure the accuracy of a result [...]

Both computation- and memory-intensiveness of deep learning models have made the deployment of model inference on edge devices with limited resource and energy budget challenging. Non-Volatile Memory (NVM) based in-memory computing has been proposed to reduce data movement as well as energy consumption, which could alleviate the challenge. Racetrack memory is a newly introduced memory technology. It allows high data density fabrication and thus is a good fit for in-memory computing. In order to facilitate the deployment of deep learning models on edge devices, we present an racetrack memory based in-memory integer multiplication, which is one of the core operations in compressed deep learning models. The presented multiplication can be constructed efficiently using racetrack memory technique, and perform the logical operations based on the memory cell with partial reuse of the peripheral circuits. In addition to the multiplication architecture, we also propose and apply a novel write optimization method to the integer multiplication, which transforms the required write operations to shift operations for performance and energy efficiency. The resulting design realizes high area and energy efficiency while maintaining comparable performance with its CMOS counterpart.

A new asynchronous early output, relative-timed block carry lookahead adder (BCLA) incorporating redundant carries is proposed. Compared to the best of existing semi-custom asynchronous carry lookahead adders (CLAs) employing delay-insensitive data encoding and following a 4-phase handshaking, the proposed BCLA with redundant carries achieves 14.9% reduction in cycle time and 12.3% reduction in area with no power penalty. A hybrid variant involving a ripple carry adder (RCA) in the least significant stages i.e. BCLA-RCA is also considered that achieves 15.2% reduction in cycle time and 11.2% reduction in area over the best of existing hybrid CLARCA variants without power penalty.

Mission- and safety-critical circuits and systems employ redundancy in their designs to overcome any faults or failures of constituent circuits and systems during the normal operation. In this aspect, the N-modular redundancy (NMR) is widely used. An NMR system is comprised of N identical systems, the corresponding outputs of which are majority voted to generate the system outputs. To perform majority voting, a majority voter is required, and the sizes of majority voters tend to vary depending on an NMR system. Majority voters corresponding to NMR systems are physically realized by enumerating the majority input clauses corresponding to an NMR system and then synthesizing the majority logic equation. The issue is that the number of majority input clauses corresponding to an NMR system is governed by a mathematical combination, the complexity of which increases substantially with increases in the level of redundancy. In this context, the design of a majority voter of any size corresponding to an NMR specification based on a new, generalized design approach is described. The proposed approach is inherently hierarchical and progressive since any NMR majority voter can be constructed from an (N − 2)MR majority voter along with additional logic corresponding to the two extra inputs. Further, the proposed approach paves the way for simultaneous production of the NMR system outputs corresponding to different degrees of redundancy, which is not intrinsic to the existing methods. This feature is additionally useful for any sharing of common logic with diverse degrees of redundancy in appropriate portions of an NMR implementation.

This article presents a comprehensive survey of time-multiplexed (TM) FPGA overlays from the research literature. These overlays are categorized based on their implementation into two groups: processor-based overlays, as their implementation follows that of conventional silicon-based microprocessors, and; CGRA-like overlays, with either an array of interconnected processor-based functional units or medium-grained arithmetic functional units. Time-multiplexing the overlay allows it to change its behavior with a cycle-by-cycle execution of the application kernel, thus allowing better sharing of the limited FPGA hardware resource. However, most TM overlays suffer from large resource overheads, due to either the underlying processor-like architecture (for processor-based overlays) or due to the routing array and instruction storage requirements (for CGRA-like overlays). Reducing the area overhead for CGRA-like overlays, specifically that required for the routing network, and better utilizing the hard macros in the target FPGA are active areas of research.

Multiplication is an important arithmetic operation that is frequently encountered in microprocessing and digital signal processing applications, and multiplication is physically realized using a multiplier. This paper discusses the physical implementation of many indicating asynchronous array multipliers, which are inherently elastic and modular and are robust to timing, process and parametric variations. We consider the physical realization of many indicating asynchronous array multipliers using a 32/28nm CMOS technology. The weak-indication array multipliers comprise strong-indication or weak-indication full adders, and strong-indication 2-input AND functions to realize the partial products. The multipliers were synthesized in a semi-custom ASIC design style using standard library cells including a custom-designed 2-input C-element. 4x4 and 8x8 multiplication operations were considered for the physical implementations. The 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshake protocols were utilized for data communication, and the delay-insensitive dual-rail code was used for data encoding. Among several weak-indication array multipliers, a weak-indication array multiplier utilizing a biased weak-indication full adder and the strong-indication 2-input AND function is found to have reduced cycle time and power-cycle time product with respect to RTZ and RTO handshaking for 4x4 and 8x8 multiplications. Further, the 4-phase RTO handshaking is found to be preferable to the 4-phase RTZ handshaking for achieving enhanced optimizations of the design metrics.

A new majority and minority voted redundancy (MMR) scheme is proposed that can provide the same degree of fault tolerance as N-modular redundancy (NMR) but with fewer function units and a less sophisticated voting logic. Example NMR and MMR circuits were implemented using a 32/28nm CMOS process and compared. The results show that MMR circuits dissipate less power, occupy less area, and encounter less critical path delay than the corresponding NMR circuits while providing the same degree of fault tolerance. Hence the MMR is a promising alternative to the NMR to efficiently implement high levels of redundancy in safety-critical applications.

In the era of nanoelectronics, multiple faults or failures of function blocks are likely to occur. To withstand these, higher levels of redundancy are suggested to be employed in at least the sensitive portions of a circuit or system. In this context, the N-modular redundancy (NMR) scheme may be used to guard against the multiple faults or failures of function blocks. However, the NMR scheme would exacerbate the weight, cost, and design metrics to implement higher-order redundancy. Hence, as an alternative to the NMR, the majority and minority voted redundancy (MMR) scheme was proposed recently. However, the proposal was restricted to the basic implementation with no provision for indicating the correct or the incorrect operation of the MMR. Hence in this work, we present the MMR scheme with the error/no-error signaling logic (ESL). Example NMR circuits without and with the ESL (NMRESL), and example MMR circuits without and with the proposed ESL (MMRESL) were implemented to achieve similar degrees of fault tolerance using a 32/28-nm CMOS technology. The results show that, on average, the proposed MMRESL circuits have 18.9% less critical path delay, dissipate 64.8% less power, and require 49.5% less silicon area compared to their counterpart NMRESL circuits.

This paper presents a new approximate adder architecture which when implemented on an FPGA consumes fewer logic resources compared to accurate adders of similar size and can achieve higher or comparable operating frequencies. For 32-bit addition, our approximate adder achieves a 25% reduction in the number of LUTs utilized compared to the accurate adder with no compromise on the speed performance. For 64-bit addition, our approximate adder achieves a 24% improvement in the maximum operating frequency, and a 25% reduction in the number of LUTs utilized compared to the accurate adder (post place and route on a Virtex-7 FPGA device). We also make comparisons with the FPGA-based implementations of some well-known gate-level approximate adders, and further provide insights into the error characteristics showing that the proposed approximate adder has a reduced error range.