Deep Neural Networks (DNNs) are very powerful neural networks, widely used in many applications. On the other hand, such networks are computation and memory intensive, which makes their implementation difficult onto hardware-constrained systems, that could use network-on-chip as interconnect infrastructure. A way to reduce the traffic generated among memory and the processing elements is to compress the information before their exchange inside the network. In particular, our work focuses on reducing the huge number of DNN parameters, i.e., weights. In this paper, we propose a flexible and low-complexity compression technique which preserves the DNN performance, allowing to reduce the memory footprint and the volume of data to be exchanged while necessitating few hardware resources. The technique is evaluated on several DNN models, achieving a compression rate close to 80% without significant loss in accuracy on AlexNet, ResNet, or LeNet-5.

In Deep Neural Network (DNN) accelerators, the on-chip traffic and memory traffic accounts for a relevant fraction of the inference latency and energy consumption. A major component of such traffic is due to the moving of the DNN model parameters from the main memory to the memory interface and from the latter to the processing elements (PEs) of the accelerator. In this paper, we present DNNZip, a technique aimed at compressing the model parameters of a DNN, thus resulting in significant energy and performance improvement. DNNZip implements a lossy compression whose compression ratio is tuned based on the maximum tolerated error on the model parameters provided by the user. DNNZip is assessed on several convolutional NNs and the trade-off inference energy saving vs. inference latency reduction vs. network accuracy degradation is discussed. We found that up to 64% energy saving, and up to 67% latency reduction can be obtained with a limited impact on the accuracy of the network.

The Network-on-chip (NoC) paradigm has been proposed as a promising solution to enable the handling of a high degree of integration in multi-/many-core architectures. Despite their advantages, wired NoC infrastructures are facing several performance issues regarding multi-hop long-distance communications. RF-NoC is an attractive solution offering high performance and multicast/broadcast capabilities. However, managing RF links is a critical aspect that relies on both application-dependent and architectural parameters. This paper proposes a design space exploration framework for OFDMA-based RF-NoC architecture, which takes advantage of both real application benchmarks simulated using Sniper and RF-NoC architecture modeled using Noxim. We adopted the proposed framework to finely configure a routing algorithm, working with real traffic, achieving up to 45% of delay reduction, compared to a wired NoC setup in similar conditions.

Network-on-chip (NoC) is currently the chosen paradigm for interconnection in multicore architectures. On the other hand, the development of these architectures with thousands of cores leads to several issues regarding latency and power consumption, especially with conventional wired interconnects. Moreover, they do not support specific features like broadcast and multicast. Radio-Frequency NoC based on OFDMA seems an appropriate solution to overcome such issues, providing low latency for long communications and a significant communication bandwidth with a high spectral efficiency. It also permits a dynamic allocation of the available bandwidth among the different elements of the NoC, according to the communication needs. The routing algorithm has a significant impact on the overall performance of a RF-NoC, by diffusing the traffic in a suitable way between the wired and the wireless paths in order to improve the throughput and reduce the latency. In this paper, a threshold-based routing algorithm is proposed and evaluated for a 32×32 RF-NoC OFDMA architecture with 32 concurrent wireless channels. We demonstrate the importance to finely tune the threshold parameter to achieve a certain level of performance. Simulation results show a significant improvement in terms of latency and throughput.

This contribution describes a sensor for GHz characterization of in vitro cell culture, that overcomes the limitation in high frequency of classical bio-impedance spectroscopy. The sensor we developed enables to monitor a thin layer of approximatively 30μm of cells in their liquid culture medium for a relative permittivity in the range of 5 to 55. Here, we demonstrate the measurement principle using a Finite Element model, which has been validated with experimental response. Our sensor has a minimal sensitivity of 0.3 MHz. We also used a multiphysics model to demonstrate that this technology does not affect tissue safety for input power level compatible with a sufficient measurement signal on noise ratio. This technology will be used in experiments aiming at the exploration of biomarkers for post-implantation inflammatory reactions of active devices.

Despite the exceptional progress of MPSoC architectures, on chip communication networks remain a lock for the evolution of their performances due to the power consumption and the delay in data carrying. In this context, the wired radio frequency (RF) network on chip (RFNoC) has emerged. In this paper, we developed a library of RF component models in VHDL-AMS for time domain simulation. This library includes mainly the transmission line (TL) and the RF transceiver components such as the low noise amplifier (LNA), the mixer and the local oscillator (LO). The models consider the conventional parameters describing their performances including the non-linearities, the noise and the bandwidth of the LNA and the mixer. Leakages between ports are also considered for the mixer. The LO model considers the traditional parameters, more importantly its phase noise. The originality of the TL model is the modeling of the skin effect on a wide frequency range for time domain simulations. All the models are validated. Global simulations are performed to demonstrate the interest to accurately model the components of the RFNoC. The developed library is used here for wired RFNoC, however it can be used for all other wired and wireless RF communication system.

The goal of our work is to optimise the supply chain management of industrial assets with UHF RFID system. This allows simple identification. In this work, we try to go further and enrich the identification information with information about the conditions of the connected assets. To avoid any maintenance operation, we realise an energy harvesting circuit to provide the needed energy to the connected sensor. In this paper, we present the conception of an autonomous connected sensor, which works in UHF RFID band. We set up the global architecture of the measurement system and we focus mainly on the energy supplier circuit and its improvement.

La gestion de stocks a l’aide de tags RFID, pratique aujourd’hui courante, permet un gain de temps et de visibilite sur les activites logistiques, de l’approvisionnement a la vente des produits. Si dans certains secteurs economiques, la simple consultation par voie RFID de l’identifiant d’un produit suffit a la gestion du stock, dans d’autres secteurs, des informations plus riches relatives a l’etat du produit sont necessaires. A titre d’exemple, citons la mesure de la temperature d’un produit alimentaire, ou de l’inclinaison des bouteilles de vin gardees en cave. Pour realiser ces mesures necessaires a une gestion efficace des stocks, il est souvent necessaire d’adjoindre aux tags RFID un ensemble de capteurs geres par un microcontroleur. La technologie RFID utilisee en gestion de stocks est une technologie passive – le tag n’embarque aucune source d’energie. Pour alimenter les capteurs, leurs microcontroleurs, et realiser les mesures evoquees, la seule energie disponible provient donc de l’onde radio incidente, emise par le lecteur RFID, et qu’il faut recuperer au niveau du tag. Nous nous interessons ici plus particulierement a la RFID UHF, operant selon la norme ISO 18000-6c dans la bande 865,5 MHz – 868,5 MHz.

The radio frequency network on chip (RFNoC) is proposed as a solution to the network on chip issue. The maximizing of the number of the communication paths is required to increase the aggregate throughput. According to the configuration of the RFNoC and the organization of the repartition of the available spectral resources, the quality of the signal may be influenced. An analysis of the effect of the repartition of the spectral resources on the signal to interference plus noise ratio of the signal exchanged in the radio frequency network on chip is described in the content of this paper, where the final purpose is the optimizing of the overall throughput. When the signal to interference plus noise ratio is significantly deteriorated, some solutions are proposed to improve the quality of the transmissions.

This paper introduces flexible radio techniques inside integrated circuits in order to tackle the interconnect issue for many-core chips. We propose to take benefits from OFDMA for a RF-interconnect associated to a carrier allocation policy and adaptive modulation. A 20 GHz bandwidth is shared between 32 tile sets made of 32 tiles of 4 cores each, for a 4096 cores chip. We adopt a cognitive radio approach in order to dynamically share 1024 carriers, which avoids inter-cluster communication contention and decreases latency compared to conventional static approaches.

We propose in this paper a power adaptive zero-IF receiver based on a wide-band Low Noise Amplifier (LNA) dedicated to wireless home communications operating from 0.8GHz to 11GHz. Two different operation modes (low power consumption mode and high performance mode) controlled by bias conditions are applied to this LNA. The bit rate error (BER) estimated by the Q-factor of eye diagram is used as mean to measure the link quality of receiver. We show that by manipulating the two operating modes of the LNA, the receiver's power can be reduced at least by 80% under favorable communication scenarios.

A paradigm shift is apparent in Chip Multiprocessor (CMP) design, as the new performance bottleneck is becoming communication rather than computation. It is widely provisioned that number of cores on a single chip will reach thousands in a decade. Thus, new high rate interconnects such as optical or RF have been proposed by various researchers. However, these interconnect structures fail to provide essential requirements of heterogeneous on-chip traffic; bandwidth reconfigurability and broadcast support with a low complex design. In this paper we investigate the feasibility of a new Orthogonal Frequency Division Multiple Access (OFDMA) RF interconnect for the first time to the best of our knowledge. In addition we provide a novel dynamic bandwidth arbitration and modulation order selection policy, that is designed regarding the bimodal on-chip packets. The proposed approach decreases the average latency up to 3.5 times compared to conventional static approach.

A design methodology of reconfigurable distributed low noise amplifier (RDLNA) dedicated for wireless home communications operating from 0.8GHz to 11GHz is presented in this paper. This RDLNA is suitable to operate in two different operation modes: low power consumption mode and high performance mode. The used technology is 0.15μm InGaAs Active Layer pHEMT Process provided by TRIQUINT. The circuit is composed of six unit gain cells. Each cell is mounted in cascode topology. The design and the simulation results are detailed and commented. In low power consumption mode, the RDLNA has a gain of 14.0±0.3dB a noise figure (NF) of 2.4dB on average and a power consumption of 15.4mW (1.0V). In high performance mode, it demonstrates a gain of 19.8 ± 0.2dB, a NF of 1.7dB on average and a power consumption of 94.0mW(2.0V).

L'une des solutions potentielles pour ameliorer ou eventuellement remplacer les reseaux d'interconnexions au sein des systemes sur puce est l'utilisation des interconnexions RF. Dans ce papier, nous traitons de l'impact de la ligne de transmission sur la qualite du signal y circulant. En effet, la variation de l'attenuation que subit le signal, liee entre autres a l'effet de peau et la legere desadaptation de la ligne, va influencer directement le rapport signal sur bruit au niveau de chacune des voies en reception du reseau.

This paper describes a simple technique for on wafer passive multi-port circuits characterization. This method gives an efficient measurement of the scattering S-parameters of these devices at their ports reference planes. Furthermore, it provides cost saving in terms of used wafer surface and equipments by using an universal two-port Vector Network Analyzer (VNA). This method is applied to the characterization of a branch-line coupler designed on a lossy silicon substrate at millimeter waves (30 GHz). The de-embedding and the experimental procedures are presented in this paper. The experimental measurements extracted from our method show a good agreement with those made with a four-port VNA.

In this paper, we propose a new model of skin effect in time domain to perform mixed simulations using VHDL-AMS. It is used for RF interconnects but can be implemented in other applications. The skin effect is described by the resistances behavior as a function of square root of the frequency. We use the Laplace domain to have an access to the frequency in a time domain simulation, and to approximate the square root of the frequency into a ratio of two polynomial functions. We use an algorithm of software searching to minimize the maximum error. Then, we compare the results of a time domain simulation of voltage attenuation with those of frequency domain ones. The model has been validated on a wide frequency range.

In the context of future System on Chip (SoC) there is a need for efficient tools to explore the capabilities of future Network on Chip. In this paper we present a behavioral model of a RF-Interconnect system which can offer an alternative to classical global interconnects. The model was developed with VHDL-AMS. The simulation results are compared to electrical ones, and show good agreement. The new transmission line model takes into account the lossy mechanisms inherent to silicon technology.

In order to perform an accurate design, in particular in non-linear circuit, the equivalent circuit of inductors must be precisely described in a wide frequency band. Many models have been proposed to describe the behavior of inductors on lossy substrate. They consist of a great number of elements, often suggested by physical phenomena. Most of them cannot be extracted from measurements. In this paper, we propose a model composed only of elements that can be analytically extracted from measurement results.