Epilepsy affects approximately 50 million people worldwide and reduces the quality of life of these patients. This work presents an embedded system to alert the patient of an imminent seizure. This system classifies heart rate variability signals to detect an imminent seizure and alert its user. We employed time domain, frequency domain, and spectral density analysis to obtain data on heart rate changes. We then used a support vector machine to classify these signals and aid decisionmaking regarding the issuance of the alert. The embedded system can predict a seizure with a processing time of four minutes and an accuracy of 73.9%.
This paper presents a novel reflection amplifier architecture based on a hybrid coupler for D -band operation, designed for active reconfigurable intelligent surfaces (ARIS). The design uniquely integrates dual reflection amplifiers with dual-layer tuning mechanisms, combining internal varactors and capacitance-loaded transmission lines (CLTL), for precise phase control (120) and stable gain (6-11 dB). Implemented in 22 nm FDSOI technology, it achieves a compact 0.304 mm2 area and a low power consumption of 11.2 mW. The proposed solution offers significant advancements in efficiency, compactness, and phase control over state-of-the-art designs, making it ideal for next-generation communication systems.
This work proposes a high-precision, low-voltage delta-sigma modulator (DSM) for battery-powered applications. A novel low-voltage strategy, which adopts the power supply VDD as the common mode voltage of the input signal, is adopted to increase the signal amplitude. To properly handle signals whose common mode is VDD, a floating inverter amplifier based on capacitor stacking is proposed. Furthermore, a cascode structure is also introduced to boost the gain. Post-simulated in 55-nm CMOS under a 0.6-V supply, the DSM achieves 92.3-dB SNDR while only consuming 2.55 mu W at a signal bandwidth of 1 kHz. This corresponds to a state-of-the-art Schreier figure-of-merit (FoM) of 178.2 dB.
Vision Transformers (ViTs) have significantly advanced computer vision tasks by utilizing self-attention mechanisms. However, their high memory and computational demands pose challenges for deployment on edge devices. While most transformer accelerators prioritize optimizing the self-attention module, the feed-forward network also demands considerable computation. Additionally, hardware utilization and data reuse across dataflows in transformers remain underexplored, despite their potential to significantly boost performance. In this paper, we present a high-utilization vision transformer accelerator with flexible dataflow, optimized specifically for the linear layers in ViTs. Our approach introduces a tile size search strategy and implements intra-layer parallelization at the tiling level to maximize hardware utilization, along with a DRAM access analysis across various computation orders to enhance data reuse. The design features three pipelined transformer GEMM engines for head-level parallelism, supporting flexible dataflows during linear operations, and incorporates a resource reuse strategy to minimize hardware overhead during non-linear operations. The accelerator achieves a 2.77x speedup over [1] with 100% hardware utilization on DeiT-Tiny. It operates at 1000 MHz using TSMC 40 nm technology, delivering a throughput of 384 GOPS and an area efficiency of 116.79 GOPS/mm(2) across a 3.29 mm(2) area.
This paper demonstrates adaptive power supply rejection ratio (PSRR) and bandwidth enhancement using entirely analog adaptive gain boosting (AGB) and adaptive Miller compensation (AMC) for a high-efficiency output capacitor-less (OCL) LDO. Performance is enhanced only when significant load current is demanded, maximizing efficiency throughout the load range. Fast transient response is also achieved by implementing adaptive headroom extension (AHE) and slew rate enhancement (SRE). The proposed mechanisms are achieved using purely analog sensing, enabling seamless mode transitions without the need for external control. The LDO achieves a PSRR better than -80 dB and 99.24 % efficiency at 20 mA load current. The proposed adaptive techniques provide a dynamic boost of over 20 dB for PSRR and more than 10 x for bandwidth while maintaining >90% efficiency throughout the 10 mu A to 20 mA load range, resulting in superior figures of merit compared to state-of-theart low-power LDOs.
In joint communication and computation (J2C) networks, the nonlinearity of power amplifiers (PA) is used for neural network computing. Only the out-of-band (OOB) distortion needs to be compensated to meet transmission standard requirements in modern 5G and beyond communication systems, while the in-band distortion is kept. Since the OOB linearization has fewer tasks than a classical DPD, it is worth studying if an OOB digital pre-distortion (DPD) has a better complexityaccuracy trade-off than a classical full-band DPD. In this paper, we make a thorough study on the complexity of existing OOBDPD techniques and demonstrate their advantages upon fullband DPD in J2C network. We further propose a new scheme of OOB-DPD with reduced sampling rate.
We propose a technique to suppress the noise of Trans-Impedance Amplifiers (TIAs) in an integrated streak camera for repeatable input signals. This approach requires only a minor modification to the sensor architecture, involving the addition of a single power supply connected to the column buffer of the sampling cell. The noise rejection mechanism operates independently of the system's effective bandwidth. Simulation results demonstrate a reduction in TIA noise from 5.2 mV to 0.31 mV, which corresponds to the fundamental limit imposed by thermal noise on the sampling capacitor (kTC noise). As a result, the signal-to-noise ratio improves by more than an order of magnitude, achieving over a tenfold enhancement with an acquisition time of just 20 mu s, enabled by the on-chip analog averaging feature. This noise reduction capability enables the detection of low-light signals, allowing the system to accurately measure optical pulses containing as few as 300 photoelectrons with a signal-to-noise ratio (SNR) exceeding 10 and a full width at half maximum (FWHM) of 200 ps.
This paper presents a self-calibrating 1-bit phase shifter for 120 GHz reflect array antennas, designed to maintain a stable 180 degrees phase shift across process and temperature variations. The system integrates a differential hybrid coupler, switches, peak detectors, and a digital control unit. The proposed phase shifter, along with a calibration unit, is designed in a 65 nm CMOS process. Simulations show a phase error of less than 1.14 degrees and a gain error of less than 1.04 dB with proposed calibration across process and -25 degrees C to 75 degrees C temperature variation. The layout occupies only 0.12 mm(2) on-chip active area, small enough to fit under the antenna unit cell of a reflect array.
In this paper, the design of an integrated circuit for high Q-factor measurement is proposed. As the Q-factor can be measured by using an integrated circuit, it gives the possibility of an on-chip or an in-situ measurement. The proposed circuit is designed in a CMOS 0.35um technology. Simulations in different process corners have been made. The simulation results have shown that a Q-factor as high as 106 can be measured with covering frequencies ranging from 0.1 to 1.5MHz, a relative measurement error of no more than 0.01% and power consumption around 23mW in taking process corners into consideration.
This work presents the design of a rectifier for ultra-low power radio frequency (RF) energy harvesting. The rectifier utilises native nMOS based diodes operating in weak inversion. Sizing the nMOS transistors and charge capacitors (C-c) becomes critical for operating in the sub-threshold region and for rectifying low input power-voltage. Simulations of a single stage rectifier exhibit a maximum output voltage (V-DCout) using transistors with an aspect ratio of 100 mu m/500 nm and charge capacitors above 10 pF. In the case of a 10 stages rectifier, the output voltage exhibits a maximum value with an aspect ratio of 100 mu m/500 nm. The rectifier was fully characterised using different loads (200, 270, 470 k ohm, and open circuit), and over a frequency range of 0.5 GHz to 4 GHz. The rectifier was fabricated in standard 180 nm TSMC. Measurements are in line with simulations, achieving a peak V-DCout of 2.5 V at 0 dBm input power.
Patients with severe heart failure could benefit from Left Ventricular Assist Devices (LVAD) that temporarily restore cardiac function prior to heart transplantation. The FlowMaker (R) intraventricular flow accelerator offers an innovative approach to heart failure care, based on an intraventricular pump. Until now, the pump parameterization relies on echocardiographic monitoring, limiting real-time adaptation to patient needs. This study presents a new intracardiac impedance measurement system for continuous ventricular function monitoring. This article details the experimental setup to acquire intracardiac impedance signals alongside traditional biomechanical and electrophysiological signals, during an experiment on ewe model. Preliminary in vivo results suggest that the intracardiac impedance signal is prone to provide the necessary time features for pump parameterization.
This paper extends the design theory of the serial - parallel (SP) switched-capacitor AC-DC voltage down-converter for micro-watt electrostatic vibration energy harvesting from previous studies to the Dickson converter. The average input current of an ideal Dickson converter and the power loss of a realistic one are formulated to model the output power and efficiency of the Dickson converter. The optimum clock frequency is determined to maximize the output power at a target output voltage. These two switched-capacitor AC-DC voltage down-converters were designed and fabricated with 2.5 V, 5 V and 12 V transistors in a 250 nm CMOS process to validate the model. When the equivalent circuit model for the electrostatic vibration energy transducer had a voltage amplitude of 10 V for the open-circuit voltage and an output impedance of 1.6 M Omega, the Dickson converter was measured to deliver an output power of 2.6 mu W at an output voltage of 1.0 V with a power efficiency of 33 %, which was 9 % higher than that of the SP converter. The circuit occupied an area of 0.4mm(2).
The theoretical design of complementary-diplexer-based input-absorptive analog filters with co-integrated lowpass-single/multi-passband response is reported. These filters are derived from the direct application of a normalized-lowpass-to-lowpass-single/multi-passband frequency transformation over an equivalent normalized lowpass filter prototype. The lowpass-single/multi-passband filtering transfer function of their main channel is thus obtained by splitting a lowpass-type transmission range in a lowpass band and one or various passbands, whereas the resistively-terminated auxiliary channel exhibits the frequency-opposite single/multi-passband-highpass response. As such, the out-of-band analog-signal power reflections coming from the main channel are dissipated by the resistor loading the auxiliary channel, so that input-absorptive capabilities are gained. The theoretical operational foundations of the engineered class of input-reflectionless filter with composite filtering functionality by using a coupling-routing-diagram formalism are described. Its extension to two-port-quasi-absorptive filter realizations and a synthesis example with additional out-of-band transmission zeros (TZs) are also shown. Moreover, the design of a UHF/VHF-band second-order lowpass-dual-passband filter in a lumped-element circuit with absorbed inverters is detailed. Practical aspects, such as yield analysis, effect of the quality factor of the lumped elements, and electromagnetic (EM) simulations of a realization in a planar substrate with the measured $S$-parameter blocks for the selected commercial lumped inductors, are also presented.
The large-scale application of Computer Vision (CV) has generated a vast amount of image data, posing challenges for transmission and storage. Compressive Sensing (CS) reduces transmission costs by sampling and compressing images, but low sampling rates cause severe degradation, harming downstream CV task inference. To address this, this paper proposes a featureoriented reconstruction approach using a feature reuse network and adversarial learning to enhance classification accuracy at low sampling rates. It introduces a classifier to ensure that the label of the reconstructed image aligns with the original. Experimental results show that the classification accuracy of images reconstructed by the proposed method on CIFAR-10 and Imagenette datasets outperforms existing methods across varying sampling rates, with a maximum improvement of 18.23% and 15.15% in average accuracy, respectively. The proposal effectively preserves the information necessary for classification under low sampling conditions, which is suitable for resource-constrained scenarios requiring efficient image transmission and recognition.
This paper deals with a digital-gate-based ultra-low-power ultra-low-voltage (ULV) operational transconductance amplifier (OTA) topology. The proposed amplifier uses inverter-based topologies with a NOR3-based common-mode feedback (CMFB) to reduce supply voltage, increase scalability, and improve performance. The architecture has been designed for a 65-nm CMOS process, and it has shown a gain of 32.75 dB, a state-of-the-art gain-bandwidth product of about 102.45 kHz, and a phase margin of 67.12 degrees, with an output load capacitance of 100pF. The CMFB mechanism implemented here ensures a common-mode rejection ratio (CMRR) of about 34.87 dB. Additionally, the power consumption of the proposed OTA is 66.63nW, and its area is about 8.4 mu mx3.6 mu m.
This paper presents a novel Delta Sigma ADC architecture designed to meet stringent requirements for high SNDR at moderate bandwidths. Based on a sturdy MASH Delta Sigma with NSSAR second stage, the architecture achieves noise cancellation by virtue of the NS-SAR feedforward property. The NS-SAR stage also benefits from significantly reduced design constraints due to the additional noise shaping provided by the first stage, allowing a more power-efficient design. An innovative dynamic amplifier is proposed to optimize the design trade-off in the first integrator. Simulation results demonstrate excellent performance, achieving 500 kHz bandwidth and 90.3 dB SNDR with a power consumption of 1.633 mW, yielding a FOMSc of 175.2dB.
Delta sigma modulators (DSMs) are a very attractive solution to build flexible high resolution transmitters needed for future massive multiple-input multiple-output (mMIMO) systems. The main challenge in this architecture is its out-of-band (OOB) noise which can be addressed by using FIRDACs. This paper proposes a joint design of the DSM and FIRDACs. The coefficients of the latter are chosen using a multiobjective optimization approach which takes into account the DAC and the DSM noise. The proposed solution is simulated for a 400 MHz 4-Channel signal. Compared to a classical design approach with similar complexity, it achieves 2.86 dB and 16.19 dB improvements for respectively the adjacent and the alternate channel power ratio and error vector magnitude (EVM) of 1.02.
This paper presents a frequency-controlled nanoampere current reference (IREF ) circuit capable of generating reconfigurable output currents, ranging from 2.3 nA to 205 nA by varying the clock frequency from 110 kHz to 10 MHz. Simulated in the Cadence generic 45nm (gpdk045) CMOS process, the dynamic IREF achieves a temperature coefficient (TC) of 47.2ppm/degrees C over -40 degrees C to 125 degrees C under nominal conditions without requiring any trimming. It shows a line sensitivity (LS) of 1.23%/V with a minimum supply voltage of 1.1V, and maintains stable operation with current ripples under 0.2%pp, achieved through a 2nd-order current-mode low pass filter (LPF). The wide current range combined with low ripple performance makes the design particularly suitable for low-power applications. Additionally, the design parameters of the dynamic IREF are fully disclosed to facilitate replication and support further research.
Stochastic computing (SC) is a computational paradigm that employs stochastic bitstreams to represent data. Although SC has demonstrated success in numerous tasks, the computation of functions with classical stochastic bitstreams remains severely affected by low accuracy and high latency. Consequently, computing complex tasks, such as the computation of nonlinear activation functions of neural networks, is a significant challenge. To address this issue, we propose the CORDIC-SC algorithm for low-latency and high-precision nonlinear function computation and design a logic circuit unit for bitstream format input. The experimental result shows that the proposed unipolar method is 7.7x more energy efficient and 10.2x more area efficient than the existing SC method while maintaining the same degree of accuracy. In addition, the proposed bipolar method is capable of reducing the error by 99.995% while maintaining the same latency.
This work presents a robust multi-bit compute-in-memory architecture using a 4T1C eDRAM cell. The proposed 4T1C eDRAM has a decoupled read and write port. Hence, avoid the destructive read operation to support multiple row activation during the MAC operation and enhance the system's throughput. The throughput of the proposed architecture is 4.09 TOPS, which is 20x higher than the state-of-the-art. The `345' relative PVT variation of the proposed architecture is 2%, 4.26x lower than the state-of-the-art. The energy efficiency of the proposed architecture is 8.71 TOPS/W at 0.8 V supply voltage. The achieved inference acuracy is 97.4% for MNIST data set. The FoM of the proposed architecture is 17.81, which is 172x higher than the state-of-the-art.
