Electrostatic discharge is always an area of concern in reliability and production of ICs. To design effective ESD clamps, knowing how the clamp turns on and operates during an ESD event is critical. This cannot be done with S-parameters or any other type of typical RF characterization. Transmission Line Pulsing, TLP, is a high-speed system that mimics an ESD event with a very short flat pulse (100 ns is typical). This allows in situ measurement of the voltage and current at the DUT during an ESD-like event. This paper will give an introduction into the theory (which is based on time domain reflection), configuration and uses of TLP. Different TLP configurations will be reviewed, and each configuration an IV curve for the DUT response is discussed. Calibration and correction will be explained which are done in the time domain. These provide the voltage and current references. The importance of the TLP load line will be discussed and its application to DUT characterization of turn-on and snap-back. Finally, characterization with pulses shorter than 10 ns, Very Fast TLP, are presented and its hurdles to accurate calibration.

Charged Device Model testing is confronted with high operating frequencies driving CDM to lower voltage levels and by high-density packages with ever smaller ball/pin pitches. A new CDM discharge head design meets these challenges by making DUT contact first and then an internal spark discharge occurs in a controlled environment.

New two two-pin ESD testers are capable of doing both Transmission Line Pulse (TLP) and Human Body Model (HBM) testing at wafer level. These systems facilitate using test structures to link fundamental circuit element parameters measured with TLP and expected HBM results on final products.

“No Connect” pins were exempted from HBM testing due to tester delivery path parasitics producing an unintended CDM-like overstress. A modified two-pin HBM tester has been build that reduces overstressing to a level were valid testing of No Connect pins and high voltage pins with snapback protection is possible.

This work describes an ESD empirical simulation flow for circuits containing snapback-based devices. Regular ESD transistors SPICE models were combined with empirical models, based on TLP measurements. Behavioral language VerilogA code has been used to add measured characteristics of the transistor at triggering voltage dependent on simulated gate voltage.

Instead of using a pin group approach as defined in the current HBM standard JS-001, stressing statistically determined pin pairs can drastically reduce the stress count and the stress time. The correlation of different HBM test methods is discussed with different examples, proving the wide applicability of this approach.

TLP characterizations are derived from analyzing pulses going to and reflections coming back from the DUT. Unfortunately, secondary reflections echo between the TLP pulse generator and DUT producing extraneous stresses. Reflection control techniques are reviewed and new methods using reflection cancellation for VF-TLP, which prevent inverted voltage re-reflections, is described.

ESDA Work Group 5.6, HMM (Human Metal Model), has conducted a round robin study using the HMM Standard Practice to determine reapeatability and reproducibility. Eight labs, using various ESD guns, 50 ohm and two-pin HMM pulsers show a range of results that highlights the variability allowed in the required waveform.

Progress toward a joint ESDA/JEDEC CDM standard is described. A “10 ohm CDM” test head experiment comparison to JEDEC standard testing is discussed. A second experiment (field plate dielectric thickness variation / ESDA test head) is described. Oscilloscope bandwidth / filtering, test head response, attenuators, and module effects are discussed.

The concept of selecting a reduced sample of identical pins for reducing the HBM ESD test times is introduced. It is shown that when the reduced sample has a tight failure distribution above an HBM specification level, the sampling approach can be accurate and will save HBM ESD test time.

Electrostatic discharge (ESD) testing of integrated circuits (ICs) is necessary to ensure that the products can withstand several types of ESD threats, including those encountered in the factory and in the field. This study discusses the testing of components with electrostatic stress waveforms that were originally designed for predicting system failures in the field. IC manufacturers are struggling to obtain reliable data when applying system tests to their components due to interface and repeatability problems found with this form of evaluation. To alleviate these problems and some of the confusion, a new test methodology has been designed and implemented. It is used for testing individual components that have pins that are to be connected to the external ports on a completed design. This study reports on a new method that solves these IC testing problems and compares it to the current approach most often employed.

HBM tester parasitic capacitances are shown to degrade the current pulse rise-times on the ground path return. Rise-times longer than allowed in the HBM specification may cause failures on devices with transiently triggered ESD protection networks. Two pin HBM testing and TLP measurements have verified such failures as being induced by tester parasitics. Updates to the HBM standard are needed to address this testing issue.

HMM data illustrates the usefulness of collecting current pulse waveforms during HMM testing. Waveforms revealed failures before leakage measurements would show device failure. With capacitively coupled devices, Time Domain Reflectometry, (TDR), can be used to detect part failures in addition to extracting this information from HMM pulse waveforms.

Two-pin HBM testing has been recommended in recent publications to avoid tester related problems. This paper discusses the advantages and disadvantages of two-pin HBM testing compared with testers that use relay matrices for pulse switching to DUT pins. Changes to HBM standards for two-pin testing are recommended.

The ESD Associationpsilas Workgroup 5.5 subcommittee is conducting a round robin study to determine the repeatability and reproducibility of measurements made the current VF-TLP Standard Practice. This study involves seven test sites with eleven different test structures evaluated at each site. This paper summarizes these findings to date.

Device testing using an IEC-compliant hand-held 150 pF/330 Omega discharge gun was compared to a 50 Omega IEC waveform pulser. Current waveforms were recorded and components tested with both pulsers. To understand effects of different pulse source impedances, the 50 Omega pulser was modified to operate at 100 and 330 Omega delivery impedances.

Obtaining TLP-type data from properly instrumented HBM systems is demonstrated. Parameters similar to those extracted by TLP are measured from HBM pulses. The new concept of "DUT snapback impedance" is introduced to explain DUT response to 1500Omega HBM pulses and various impedance TLP systems. Observed stresses with HBM, not present in TLP, may account for some HBM-TLP miscorrelations.

Small anomalies found in pulses from HBM testers have been the subject of much recent research. Reported anomalies have been shown to adversely effect HBM testing. This paper reviews the cause of many anomalies and describes an HBM pulse generation system that eliminates or reduces these anomalies to negligible levels.