This paper discusses the so called Pressing Probe Needle (PPN) technique for characterizing out-of-plane mechanical stress sensitivity of arbitrary semiconductor devices, implemented on a standard parametric test system. By utilizing a motorized probe positioner and a force calibrated standard tungsten parametric probe needle, this fast and highspatial-resolution technique provides valuable insights into mechanical stress effects of process and device layout options. Such results are highly beneficial for high-precision analog circuit design and layout optimization.
Accurate modeling of the gate-drain capacitance C gd for HV LDMOS transistors is important but is challenging because of its strong bias dependence. We present an improved C gd model, based on the physics that the drift region under the poly-gate is fully depleted at high V dg , and validate our model against gate charge measurements for both n-and p-type 90V LDMOS transistors.
A new, cage-like structure is presented and is shown to be able to electrically identify a probe needle that has fallen slightly off its probe pad, even when the standard probe resistance structure (pads shorted together) reports “good” probe resistance. Using both structures together enables a more accurate evaluation of a probe system’s capabilities. Both test structures were used to compare three types of probe cards, reporting the smallest probe pad size that provides 100& probe yield.
The goal of the study is to monitor the device’s response during laser injection while being able to track pre- and post-attack conditions. We show the irradiation power affects the STT-MRAM behavior. Our electrical/optical setup enables to know the memory cell behavior to study real-time laser attack countermeasures and device reliability. We have highlighted the possibility to switch, to degrade or even to destruct the cell, depending on the laser power.
The variability of the neuronal function device of a metal oxide semiconductor-gated PNPN diode was evaluated. The variability of neurons is known to affect the inference accuracy of spiking neural networks (SNNs). The device has stochastic operation on its own, and the spike frequency can be controlled by the gate voltage, which has the possibility to improve the accuracy of SNNs.
In this study, we propose a novel transistor modeling method using machine learning techniques, with a focus on extrapolation performance. Our method leverages knowledge from a base model that is related to the target model, instead of relying solely on device-specific information. The results show that our approach outperforms other transistor modeling methods based on machine learning, particularly in modeling similar but different transistors that belong to the same device family. Our method was able to reduce the root mean squared error (RMSE) by up to 80.0% compared to other methods.
In silicon technology, Schottky diodes mainly exhibit high current levels, and attempts are regularly made to reduce these by introducing 2D layers between the metal contact and the silicon. Defects in such interfacial layers, from weakly bonded structures to actual pinholes, can lead to high, localized metal-semiconductor Schottky currents. Using the example of diodes with an interfacial layer of pure boron (PureB) between an aluminum metallization layer and the Si, a signature for such ‘‘nano-Schottky’s’’ is determined by evaluating the results of several different test-structure arrays and measurement techniques. An adapted bipolar-type measurement is introduced as an additional method to determine whether any high current characteristics originate from a low Schottky barrier height over the entire diode surface or from a localized nano-Schottky structure.
Models for parasitic capacitances in the MOSFET overlap region are developed for circuit simulation. In particular, the overlap capacitance ($C_{\mathrm{o}\mathrm{v}}$) model considers the modulation of the overlap length due to the dynamic depletion of channel/LDDjunction, which is the physical origin of the $C_{\mathrm{o}\mathrm{v}}$ bias-dependence. The models are implemented in Verilog-A, and incorporated in a MOSFET model for circuit simulation. Reproduction of device simulation results and RF-CMOS gatedrain capacitance measurements are verified.
This paper presents the demonstration of an antiambipolar switch (AAS) using a ZnO-dinaphtho[2,3-$b: 2^{\prime}, 3^{\prime}$ ' $f]$ thieno $[3,2-b]$ thiophene (DNTT) heterojunction structure. The proper combination of n-and p-type thin-film semiconductors achieved a high peak-to-valley ratio of $\sim 10^{5}$ at a low process temperature compatible with the back-end-of-line process. Using the electrical characteristic of positive-to-negative transconductance switching at the peak current point, a frequency doubler was implemented with only one device. The excellent electrical performance of the ZnO-DNTT AAS device resulted in a high conversion gain of $-5 \mathrm{~dB}$ and an output frequency purity of 97 %.
Ferroelectric Tunnel Junctions (FTJs) operating as memristors are promising electron devices to realize artificial synapses for neuromorphic computing. But the understanding of their operation requires an in-depth electrical characterization. In this work, an inhouse experimental setup is employed along with novel experimental methodologies to investigate the largesignal (LS) and small-signal (AC) responses of FTJs. For the first time, our experiments and physics-based simulations help to explain the discrepancies between LS and AC experiments reported in previous literature.
In this study, a unique supercritical fluid (SCF) treatment is utilized to improve the resonance properties of thin film bulk acoustic resonators (FBARs) composed of a piezoelectric material of AlN. In an etching process of the sacrificial oxide, FBARs suffered from severe surface tension of etching acid solvent, resulting in structural bonding and residues generation. These impact on FABR’s structural integrity would influence its resonance properties. Therefore, a SCF treatment with low surface tension and high penetrability can effectively carry out residues from the release gap in a FBAR, observed from SEM images. The results show that the reflection coefficient, the quality factor, and the effective coupling coefficient are all improved in FABRs.
On semiconductor IC chips, non-functional test structures are often designed along with the functional circuits in order to monitor the process quality even when the wafers are running in the line. This paper introduces an inline electrical test structure to monitor a systematic gate-source/drain short defect that degrades chip product yield. This area efficient, test time friendly, and insightful test structure is ideal to monitor process quality for the forementioned failure mode and help with the diagnosis of chip functional failures.
A practical test bench for dry electrode bio-signal instrumentation amplifier is presented and demonstrated. By modifying the on-the-shelf single-ended to differential amplifier, the common-mode rejection ratio and distortion under electrodes offset scenario can be characterized. The other essential parameters such as input impedance and power supply rejection ratio can also be determined.
Using a test structure chip designed to assist in process development for reference electrode fabrication for integrated electrochemical sensors, this paper reports measurements of Greek cross test structures and compares them to measurements of bridge resistor structures on the same chip. The correct application of these structures requires careful consideration of the measurement parameters to provide accurate results and different force current values have been investigated. Results from platinum structures suggest there is measureable variation in the feature size when Greek cross results are used to extract electrical critical dimension from the bridge resistor measurements. Similar measurements of silver structures were less conclusive. While the bridge structures show a significant effect of oxidation of silver which has been exposed to air since fabrication, the Greek cross results are highly variable and may not be reliable.
Reverse electrowetting on dielectric (REWOD) has emerged to be a promising energy harvesting technology from low frequency vibrations. This study aims to use test structures to characterize a unique form of REWOD using a coplanar electrode configuration. This configuration allows for better versatility in system integration, device packaging and applications.
The use of polysilicon heater structures provides a useful tool for fast NBTI monitoring of wafer level reliability in production measurements. It could reduce device relaxation in NBTI measurement without special ultra-fast test equipment. In this work NBTI characterization from a parametric tester using polysilicon heater test structures for 1.2V PMOS devices placed in the scribe line of a 65 nm BCD technology was performed with real-time feedback temperature control methodology without changing the chuck temperature to realize NBTI reliability assessment with a short test time.
Computing-in-memory (CIM) is a promising technique for energy-efficiently conducting the massive amount of required multiply-and-accumulate (MAC) calculations in neural networks (NNs). The read-decoupled 8T (RD8T) SRAM cell is popular in the CIM designs because of being read disturbance free. However, local process variations may lead significant errors to the CIM results. This work proposes an accurate on-chip test circuit design for characterizing the output current of every RD8T SRAM cell in a 8-kb RD8T SRAM array fabricated in 90nm CMOS. The experimental results show the detailed and accurate spatial distribution of the RD8T cells which helps optimize the CIM circuit design.
This article presents a bitcell of a static randomaccess memory (SRAM)-based physically unclonable function (PUF) with quadruple-size transistor, which reduces the tail’ of mismatch distribution after hot carrier injection (HCI) burn-in. A statistical mismatch distribution model after HCI application for a certain time is proposed by combining native mismatch distribution before HCI and mismatch shift distribution after HCI. Model calculation shows that quadruple-size transistor SRAM PUF needs 15-min HCI burn-in time to achieve cryptographic level requirement, which is more than 3 times shorter than normal-size transistor SRAM PUF of 46-min. The effect of utilizing the quadruple-size transistor with respect to HCI burn-in for stability reinforcement is also confirmed by measuring chips fabricated in a 130-nm CMOS process. Experimental results show that the ‘tail’ in mismatch distribution is significantly eliminated after 18-min HCI burnin time of quadruple-size transistor SRAM PUF, which meets our expectations. The presented statistical model also matches the measurement data well.
Advancing highly integrated micro sensors and actuators calls for the ability to scale down three-dimensional structures while ensuring efficient electrical interconnectivity. This necessitates addressing a pressing need to develop novel techniques for shrinking components and facilitating seamless interconnectivity to the miniature structures. Here, we demonstrate a three-step fabrication method to produce 3D prints fabricated by direct laser writing (DLW) via two-photon polymerization (TPP), with multisided evaporated metal patterns. The three steps consist of printing the core structure and shadow mask shell (SMS) on sacrificial Dextran 70, evaporating metal onto the desired side(s), and then releasing the core and SMS in water. To showcase this process’ capabilities, we produced a simple characterization structure featuring two electrical vias, an out-of-plane serpentine resistor, and four solderable electrodes. With this test structure, three firsts were achieved for the TPP community: (1) The deposition of metal patterns onto opposing sides of a DLW structure; (2) the flip-chip soldering of said structure to a PCB; and (3) the verification of electrical continuity through its two microvias.
We assessed the degradation of MOSFET and CMOS LSI circuit characteristics induced by the high temperature annealing, especially for the PZT deposition process. The test structure consists of ring oscillators having different numbers of stages and single PMOSFETs and NMOEFETs designed with $0.6 \mu \mathrm{m}$ CMOS technology. We observed the ring oscillator (RO) oscillating frequencies and the $I_{\mathrm{d}}-V_{\mathrm{g}}$ characteristics of the MOSFETs before and after the annealing post-process. The result indicated that such an annealing process involving high temperatures of around 575°C is possible unless the wiring on the CMOS components is mechanically broken. In addition, annealing temperature affected the MOSFET characteristics more than annealing times. Therefore, the effects of the CMOSMEMS monolithic integration using PZT thin films be optimized using the proposed test structures.
