Ovonic threshold switching (OTS) materials that are frequently used with a resistor (1S1R) in memory devices have been found to show controllable and reversible memory properties, which could enable new memory architectures. Here, we examine the impact of composition on the polarity-dependent memory properties of GexSe1-x OTS materials and reveal that an increase in Se content results in a higher set voltage threshold (V-th), a lower reset current (I-RST), and a higher set energy. Specifically, Ge56Se44 demonstrates two distinct V-th of 5.1 and 3.8 V, which retain after annealing at 85 degrees C for one day. We fabricated Ge56Se44 into 1000 by 1000 cross-point pillar arrays and tested 100 of them. The results demonstrated that these Ge56Se44 devices show similar memory properties with a reset speed of 1 mu s, a set speed of 50 ns, and an endurance of over 10(5) cycles. Interestingly, the Ge56Se44 pillars' reset and set states could be attributed to polarized atomic distributions. By utilizing GexSe1-x, we demonstrate a true cross-point switch-only-memory technology and provide mechanistic insights for self-selecting OTS materials.

We present a new selector only memory material, CuGeSe, with low program current, fast switch speed properties and good endurance. The switching mechanism is studied in depth and element migration is verified during the switching of the material. We also discuss application of the material for 3D Xpoint and 3D vertical memory, as well as propose a modified 1/3 V testing scheme for 3D vertical memory to mitigate leakage current and improve scaling.

We present a novel multi-level operation using multi cells on a cross-point OTS-PCM array with no need for program-verify scheme for the first time. This method can provide not only program energy reduction but also low drift property. In addition, a true crossbar array structure is implemented that is ideal for in-memory computing application.

To improve the voltage threshold (V th ), off-current (I off ), and reliability of 15nm ovonic threshold switching (OTS) selectors in one-selector-one-resistor (1S1R) devices, multilayered heterostructures (HS) of AsSeGeS and GeN were studied by varying both the thickness ratio of AsSeGeS to GeN (T OTS /T GeN ) and the number of GeN layers. Electrical results showed that all HS configurations had an increased V th and I off stability testing up to 10 11 cycles. Notably, HS devices with an increased T OTS /T GeN ratio exhibited the lowest I off values. Analysis revealed that the contributions to V th were greater from thicker GeN layers than from the interfacial barriers between AsSeGeS and GeN. Raman spectroscopy further showed that the proportion of Ge bonds changed with layer thickness, with thicker GeN layers exhibiting a higher number of Ge-Ge bonds. Optimized for 1S1R operation, 15nm HS devices achieved an I off of 0.4nA, a V th of 3.25V, and significantly improved I off cycling variance, demonstrating the potential of HS to enhance device performance.

We present a scaling study on phase change memory (PCM)-ovonic threshold switches (OTS) memory cells for storage class memory (SCM) applications. For the first time, the device size effect on the electrical characteristics of OTS-PCM cells is experimentally characterized with simulation support. It is found that the SET threshold voltage (VtS) of OTS-PCM cells increases as the device area scales down because of processinduced defects, as observed from experimental measurements and demonstrated with simulations. An optimized process is proposed and experimentally verified to minimize the VtS shift issue based on wafer level characterization. More importantly, combining the measurements and simulation, the device scaling trends down to sub-10 nanometers are provided for future high density cross-point PCM (XPCM) chips.

A constant current stress scheme is implemented for endurance study on OTS-PCM devices for the first time. It provides a feasible method to estimate the read/write endurance for cross-point PCM products, which can save testing time for chips qualification. A 256kb chip with 1E7 cycles is demonstrated that corresponds with the endurance evaluation on the doped AsGeSe OTS with doped Ge2Sb2Te5 system.

We present a trap limited model on OTS-PCM devices with the thickness effect to depict the conduction behavior. The forming process is well explained by using the effective thickness concept. Moreover, the dependence between leakage current and sub-threshold slope resulting in high density cross-point OTS-PCM application is discussed, and the successful readout from a 1Mb cross-point PCM ADM using half-v scheme is demonstrated accordingly.

We present a trap limited model on OTS-PCM devices with the thickness effect to depict the conduction behavior. The forming process is well explained by using the effective thickness concept. Moreover, the dependence between leakage current and sub-threshold slope resulting in high density cross-point OTS-PCM application is discussed, and the successful readout from a 1Mb cross-point PCM ADM using half-v scheme is demonstrated accordingly.

New phase-change materials (PCM) from single composite target, which is made of GST-225 and dopants “A+O (oxygen)” using special setup magnetron sputtering are systematically studied their potential for 3D crosspoint memory technology. The PCM’s stable cycling endurance characteristic is the critical criterion to guarantee tight $\mathrm{V}_{\mathrm {th}}$ distribution during write cycles. We propose a new PCM material for 3D crosspoint memory technology. The new material, with optimized concentration, integrated with high Indium doped AsSeGe selector, demonstrates a wide $\mathrm{V}_{\mathrm {tS}}/ \mathrm{V}_{\mathrm {tR}}$ memory window (~1.5V memory window), stable 1E7 chips level write cycles (using 400ns SET box pulse time) and extremely low $\mathrm{V}_{\mathrm {tS}}$ and $\mathrm{V}_{\mathrm {tR}}$ drift characteristic (~0V) at 85 °C/1 day in 256kbits (64kbits are tested) ADM memory arrays.

The doping effect on AsSeGe OTS materials is comprehensively studied. While B, C, S doped selectors suffer a stringent trade-off among Vth, IOFF and cycling endurance, Si and In doped selectors demonstrate an extremely low VtS (system threshold voltage when PCM is in SET state) and VtR (system threshold voltage when PCM is in RESET state) drift characteristics. We demonstrated true crosspoint operation (by half-V scheme) in a 1k by 1k cross-point ADM memory arrays from an In doped AsSeGe selector integrated with PCM with extremely low IOFF (~3nA from a total 100 crosspoint cells), wide VtS/VtR memory window (~2V main distribution memory window), 1E6 write cycles and low Vts and VtR drift characteristic (project<0.3V and 0.5V, respectively for one year) which is suggested for 3D crosspoint memory technology.

By incorporating Si into AsSeGe system, we demonstrate a 3D stackable OTS+PCM memory in a 1k by 1k cross-point memory array with extremely low V tS drift (~0V after 3 days from programming), wide V tS /V tR window (>2V main distribution memory window), high endurance (>2E11 cycles), excellent I OFF and thermal stability. So far, attempts to improve the thermal stability of AsSeGe system sacrifice I OFF and cycling endurance. We show that Si incorporation relaxes this trade-off and can greatly improve the thermal stability and cycling endurance while also achieving good I OFF . In particular the I OFF of AsSeGeSi selector is improved over the AsSeGe system for films of 20 nm.

A reliability study for phase change memory ( PCM) pillar cell is performed. We found that without a buffer layer, the PCM pillar cell shows earlier endurance failure than its mushroom counterpart, and the underlying failure mechanism is attributed to element segregation. A buffer layer between PCM and top electrode is found to substantially improve the endurance characteristics of the PCM pillar cell to greater than 1E10 program cycles. In addition, the buffer layer also provides the benefit of increased PCM threshold voltage ( Vth), which can enlarge the read window margin for the OTS+PCM 3D Cross-Point Memory array.

We present a scaling study toward lZnm node 3D Cross-point PCM (XPCM) for Storage Class Memory (SCM) applications. The low operation current, and low metal line loading resistance are desired to avoid a wide operation voltage distribution in a cross-point array. For the first time, AC threshold voltage (Vth) of 1S1R OTS-PCM was studied, which will impact the operation scheme. To achieve Tera bits per chip density, six layers 1Znm 3D XPCM with OTS showing high Vth and low leakage current, and scalable periphery circuit are required.

A reliability study for PCM and OTS intermixing was addressed. The buffer layer between PCM and OTS plays a key role in preventing PCM/OTS intermixing after BEOL processing thermal treatment. Besides cycling endurance, performance degradation due to interlayer intermixing was observed. Optimal device operation and an improved buffer layer allowed drastically improved cycling endurance from a few cycles to > 1E9 cycles.

For the first time published, high endurance OTS (ovonic threshold switch, here, TeAsGeSiSe-based) is integrated with PCM (here, doped Ge2Sb2Te5) to form a 3D stackable pillar type device. With the help of an etch buffer layer and a damage-free pillar RIE process, we achieved 100% array yield without OTS/PCM composition modification. Anneal tests show this one-selector/one-resistor (1S1R) pillar device is BEOL-compatible. We report excellent electrical performance by 1S1R OTS-PCM device; selector provides the fast turn on/off speed which enables 10ns fast RESET speed, program endurance is 109 cycles, and read endurance is higher than 1011 cycles.

New selector materials with very-low I OFF and optimum V th . based on As-Se-Ge chalcogenides are studied. An optimized composition is proposed, which achieves a good trade-off between thermal stability and cycling endurance and it is successfully integrated with PCM in a 3D stackable pillar structure. SET/RESET operation are demonstrated with ∼2V memory window. Selector is able to deliver 1mA ON current (7.9 MA/cm 2 ) and fast speed (10 ns). More than 1E12 read cycling endurance is achieved in 1S1R $(\text{OTS}+\text{PCM})$ device due to the excellent endurance of the selector.

High endurance ovonic threshold switch (OTS, here, TeAsGeSiSe-based) is integrated with phase change memory (PCM, here, doped Ge2Sb2Te5) to form a 3-D stackable pillar-type device. With the help of an etch buffer layer and a damage-free pillar reactive-ion etching process, we successfully demonstrate one-selector (OTS)/one-resistor (PCM) (1S1R OTS-PCM) pillar device without OTS/PCM composition modification. High temperature 400 °C annealing tests show this 1S1R OTS-PCM pillar device is back end of line compatible. We report the fundamental behavior of the OTS and the operation scheme of the 1S1R OTS-PCM device. The new Vth read scheme is proposed and excellent electrical performance is demonstrated. It provides the fast turn ON/ OFF speed which enables 10-ns fast RESET speed. Program endurance greater than 10 9 cycles is achieved, and read endurance is higher than 10 11 cycles.

Since the resistance switching of the transition metal oxide (TMO) resistive random access memory (ReRAM) is based on the interaction between the oxygen ions and vacancies, the unintentional oxygen/vacancy reaction should be avoided during data retention. This work demonstrates significant improvements on the retention performance by inserting a Si layer in the TiOxNy ReRAM to block the diffusion of oxygen ions through the Ti/TiOxNy interface. The mechanism and factors that influenced the HRS and LRS retention are also studied. The retention performance of HRS is correlated with its RESET level while the LRS retention depends on the programming current. The proposed Ti/Si/TiOxNy ReRAMs can switch for more than 103 cycles from array testing results.

We present the results of a primary study on an OTS chalcogenide material system (TeAsGeSi) that incorporates Se and an extra dopant. V th and I OFF are trade-off parameters that can be tuned by modification of OTS composition, thickness and process temperature. The resulting new selector material demonstrated excellent endurance (>10 10 with 50ns-pulsed 400uA On-current) and robust OTS characteristics after 350°C/30 mins annealing. The thin film could withstand 500 °C annealing.

A TiOx/TiOxNy resistive random access memory (ReRAM) with a sidewall bottom electrode (BE) is demonstrated for the first time. Several interesting characteristics that are very desirable for high reliability memory applications are observed: (1) a stable RESET and SET resistance switching window even without write verification, (2) good 250 degrees C data retention, (3) ReRAM switching instability after cycling is monitored and corrected, resulting in good reliability, and (4) using only complementary metal oxide semiconductor (CMOS) familiar materials and processes, thus very manufacture-friendly. The thickness and quality of TiOx and TiOxNy are well controlled by plasma oxidation, and a large resistance switching window (> 10x), a low operation voltage, and good reliability are realized. (C) 2017 The Japan Society of Applied Physics