For fast computation of drain current in Nano-MOSFET, we have developed a new backscattering model based on the accurate determination of ballistic and backscattering probabilities along the channel. The main elements of this model are deduced from careful analysis of transport in devices using Monte Carlo simulation. The backscattering coefficient is in very good agreement with the results of Monte Carlo spectroscopy for MOS transistors and N+/N/N+ diodes.

This paper presents an electrical analysis of mechanical stress induced by shallow trench isolation (STI) on MOSFETs of advanced 0.13 /spl mu/m bulk and silicon-on-insulator (SOI) technologies. By applying external calibrated stress, we present piezoresistive coefficients measurements on these technologies, and we compare small and long transistors electrical responses, evidencing the strong effect of source drain resistance R/sub sd/. Then, using the same approach on short devices with different gate-edge-to-STI distances, we quantitatively evaluate stress profile induced by STI and its mean value under the gate of the devices. Results are discussed to explain differences between bulk and SOI technologies, as well as between nMOS and pMOS. We show that the observed higher pMOS drain current shift is related to the process, and may be explained by doping amorphization and recrystallization effects, and not by a piezoresistive coefficient difference as usually assumed.

Plasma doping (PLAD) is an ion implantation technique under investigation to realize ultra-shallow junctions for 65 nm nodes and beyond. This technique has been modelled and is integrated in TCAD process simulation tools. The most influential parameters of PLAD have been isolated. With these parameters, a design of experiments (DOE) has been performed to interpolate a quadratic surface response model of PLAD profiles. Boron implantations were studied in the range from 1 to 8 keV and 1e15 to 5e15at/cm/sup 2/. Accuracy is very good on the whole range of parameter variations. 2D process simulations are finally shown.

Since the junctions in the most advanced CMOS devices are thinner and thinner, the influence of the surface of silicon is thus becoming significant on dopant diffusion. In this paper, based on experimental data, a methodology for calibration is proposed, taking this effect of surface into account. SIMS profiles are accurately fitted by simulation using a simple model of recombination of interstitials; the phenomenon of POED is well reproduced and validated by TCAD ID simulations. Then, the impact of POED on the PMOS performances is quantified by anticipation with 2D TCAD simulations.

The impact of the gate leakage current on long MOS transistor characterization is investigated in this paper. Particularly for first order parameter extraction, a new method is proposed here to rid the gate current on advanced technologies with thin gate oxides.In linear and in strong inversion regimes, we first demonstrate experimentally a 50/50 partition of the gate current between source and drain nodes. TCAD simulations performed for several oxide thicknesses and biases also confirm this partition. The intrinsic channel current of the MOS transistor can then be isolated to extract first order parameters, especially in the case of large area devices which strongly suffer from gate leakage. We show that this I-G correction permits to extract these parameters in a more consistent way. Finally, we evaluate the extraction error induced by the gate leakage current for varying oxide thicknesses and channel lengths.

The impact of the lateral doping abruptness (LA) of the source/drain extension still remains a polemic issue in CMOS transistor engineering. Based on dedicated simulations, it is shown that the maximum gain in on current achieved with steep profiles does not exceed 3%. Moreover, a suited analytical modeling indicates that the influence of the LA mostly resides in changing the effective channel length (Leff). Subsequently, the impact of the gate overlap is critically reviewed and actually appears to be mostly related to the analytical definition of the simulated device. Eventually, relying on a clear physical background, the analysis is carried out further to investigate the modulation of source injection properties in the framework of the backscattering theory and Monte Carlo (MC) simulations. We propose an additional injection effect that emerges at the source end potential barrier when the junction becomes very abrupt. This effect incorporated within the theory of Lundstrom enables further interpretation and understanding of the MC on-state current calculations.

In this study, body effect influence on oxide degradation is analyzed. It is found that the negative bias polarization on the n-well of a p-channel MOS transistor may induce a significant reduction of the oxide lifetime as well as an increase of stress-induced leakage current (SILC). Such a result is demonstrated to confirm the key role of hot holes on SILC and breakdown phenomena. Moreover, even if the hot hole generated at the anode are probably at the origin of SILC and can be interpreted as a catalyst of breakdown, it is undoubtedly shown that both phenomena are not directly correlated: SILC at breakdown can not be ascribed to a critical density of defect at failure.