In this paper, air gaps are presented as a viable alternative for low-k dielectrics. The emphasis will be on an integration route, which uses thermally degradable polymers as sacrificial dielectric. Some historical background on the use of these polymers is given. The main attention of this paper will however be on the mechanical integrity of the fabricated air gaps. ne latter will be supported by finite element modeling and wire bond experiments. The main conclusion from this work is that multilevel air gap stacks are not suffering more from mechanical integrity issues than porous low-k stacks. A robust integration together with some adapted design rules makes air gaps a viable option for the future technology nodes.

Amongst solutions to connect the die to the package, thermosonic wire bonding process remains widely used. However, the introduction of low-k dielectric materials, and the feature size decrease of IC chips to follow Moore's law, pose great integration challenge.This paper aims to demonstrate the compliance of the proposed modeling approach with the aids of experimental validations. 3D multi scale simulation of both bonding process and wire pull test is carried out. Using a previously validated homogenization procedure to include pad structure description even at the global scale, stress fields acting in both the gold wire and the copper/low-k stack have been evaluated and discussed. The modeling strategy also includes an in-house developed energy based analysis.For the experimental part, a wide range of wire bond trials have been performed in order to qualify the 65-nm technology node. On behalf of that, the effect of the bonding conditions has been studied. More precisely, it was found that the peeling failure rates are significantly dependant on the used wire types and their respective bonding parameters.In this paper, some numerical parameters are firstly discussed and the most suitable modeling strategy is proposed. Hence, typical results are presented, and the comparison of the peeling hazard induced by distinct bonding conditions is carried out. Simulations are then faced to experimental results and a good agreement is found. In addition to that, the complementary nature of the energy based failure criteria is highlighted through a clearer determination of the forecasted location of the failed interface in the IC stack.Finally, the simulation procedure with confirmed experimental results demonstrates its ability in design and process optimizations by providing a better understanding of pad peeling failure mechanisms.

The control of stress in silicon devices is an important issue for improvement MOS transistor performance. Some high temperature processes, like active zone silicidation or Shallow Trench Isolation [1,2] can induce motions of dislocation just by cooling the crystal down to room temperature.In this study, a single crystal model for the silicon mechanical behavior is implemented by finite element simulation using ZeBuLong (R). The constitutive equations are taken from the well known model of Alexander and Haasen [3,4] applied to each slip along the {111} planes in the < 1 (1) over bar0 > directions.The effect of silicide-induced stress is studied and the formation of defects in silicon during the cooling is discussed. Then, two layouts where the STI pattern is different are simulated and the results are checked against the leakage current measured.

Mechanical stress is a major concern in microelectronics: reliability of VLSI interconnects is mainly controlled by the stress levels. The increasing complexity of processes and the shrinking of feature sizes make necessary to use quantitative modelling in order to optimise process parameters and device geometries. We had developed a method based on the use of some finite element analysis (FEA) tools, to quantitatively determine the stress evolution along the process flow. This method allows us to simulate material deposition, etching and thermal ramping steps. It was used to monitor the stress level is in two metallic levels interconnected by a via during the fabrication. Our numerical results were analysed regarding the so-called stress–voiding phenomenon: these results allow us to point out the critical interface to focus on. All the obtained results are in good agreement with experimental observations. This method can be used to determine the evolution of the most probable void position as the geometry varies and then to optimise both the geometry and the process to minimize stress-induced voiding.

The introduction of air gaps in multi-level Cu interconnect stacks will be mandatory to achieve high performance signal propagation characteristics for advanced technology node. In this paper, air cavities were successfully introduced in a two-metal level interconnect stack using respectively a polymer and a sacrificial SiO 2 at via and metal levels. Combined with a diluted HF chemistry and specific HF diffusion pathways patterned in a SiC liner, the ability to localize the introduction of air cavities in a dedicated large electrical area was demonstrated. Electrical characteristics and mechanical simulations demonstrated the interest of the approach with respect to ultra-low K material integration issues.

Process induced stress is one of the key performance boosters to qualify advanced MOSFET technological node. 3D Finite Element simulation (FEM) is carried out to accurately model Contact Etch-Stop Layer (CESL) stress-related layout effects. Indeed, the corresponding stress field in transistors greatly depends on many parameters. Correlations with electrical measurements demonstrate results relevance. In addition to the effect of the transistor size, the environmental features of the MOSFET, such as the density of adjacent structures including dummy and Al-contact play a major role. As a result, differences in layout lead to considerably change the stress-induced transistor performance.

Resistance to the brittle cracks of single damascene line patterns on silicon wafers is investigated through three points bending tests. After loading, samples are observed by atomic force microscopy or field emission gun scanning electron microscopy, in order to detect cracks. For given load and pattern period, an appropriate numerical procedure allows calculation of the characteristic parameters of all the stress singularities, which appear along the dihedral lines at interfaces between the various materials. The most critical singularity is determined in terms of crack initiation according to a criterion combining stress intensity and energy release rate conditions. In these interconnects, crack initiation appears to be intrinsically governed by energy release conditions, so that short cracks are very difficult to initiate or propagate. The absence of detectable cracks after bending is in good agreement with this prediction.

We have studied different nitride processes to provide the best tensile layer for this application. Several Plasma Enhanced Chemical Vapor Deposition techniques, with one or two plasma frequencies (PECVD 1F or 2F), and a furnace Atomic Layer Deposition (ALD) process have been evaluated. Deposition on full sheet wafers allowed to characterize the main physical and chemical properties. In particular, the mechanical stress σ was measured by curvature method. Moreover, the sidewall step coverage (SSC) was evaluated by SEM / TEM cross section (see Table 1). The best step coverage is obtained for ALD (better than 95%) layers while PECVD 2 F (75%) presents an intermediate situation compared to PECVD 1F (55%). In parallel, the same films with different stress σ and thicknesses e distributed between 350A and 500A were tested on full flow device wafers. For each case, we measured the Ion and Ioff currents for transistors with different length (L) and a fixed width W=1μm. We then estimated the gain of Ion at Ioff =10 nA compared to a stress less reference. The performance improvement is typically proportional to the curvature created by the CESL. Therefore, it must be proportional to the product stress σ by thickness e. On Figure 1, we present for each layers, the Ion gain as a function of this product. It is clear that for a given σ*e, ALD nitrides generates more improvements than PECVD films. On Figure 2, we present the Ion improvement as a function of σ*e*SSC. In this case, the distance to the linear model is significantly improved with a R = 0.96 compared to R = 0.82 in Figure 1. As a consequence, The SSC has to be considered with σ and e to describe the gain obtained for different nitrides Thanks to these observations, we suggest a model to describe the mechanical impact of the CESL on the Si channel. As illustrated in Figure 3, especially on small devices, the tensile nitride film acts as tensile strings on the sidewall of the transistor. These strings generate a strain in the Si channel proportional to it’s surface (pressure effect). A lower step coverage yields to a lower strings concentration and a lower strain in the channel. This model is validated with both mechanical simulations studies and the electrical data of reference [5].

Continuous down scaling of the interconnect dimensions led to the introduction of copper and low-k dielectric materials. The use of such materials is challenging in the field of mechanical reliability, such as stress-induced voiding in copper interconnects and cracking of low-k dielectrics. Up to now these two failure modes were investigated separately. However, recent experimental observations tend to demonstrate the possibility of a complex interaction of both failure modes, one overwhelming or enhancing the other. In this paper a comparison of the risk of void or crack occurrence is made by the mean of finite element modelling. Further, the interaction between these two failure modes (voiding and cracking) is also studied

Mechanical reliability is widely recognized as the primary obstacle to productionization of porous low-k materials. The combination of weak bulk and interfacial properties with increasingly complex geometries poses a considerable challenge at the 65-nm node. The final solution must be sufficiently robust so as to ensure compatibility with multiple substrate types, interconnect configurations and packages. In this work, material engineering, modeling, design rule tailoring, and assembly optimization are employed to achieve required assembly reliability for both wirebond and flip-chip packages, for both bulk and SOI substrates.

In this paper, simple corrections to traditional Drift-Diffusion mobility models are derived from strained full-band Monte Carlo simulations in order to correctly account for strain effects. The validity of this approach is benchmarked upon Monte Carlo MOSFET simulations as well as experimental data featuring tensile nitride capping layers.

An analytical model for the nano-MOSFET based on the determination of ballistic and backscattering probabilities along the channel is developed. This model, validated by analysis of transport in device using scattering spectroscopy, has been used to model the strained MOSFET by evaluating the appropriate scattering relaxation times and the carrier distribution. Finally, it has been used to determine the impact of CESL on the IONenhancement.

A failure analysis based on an energy approach is used to study a two metal level structure in VLSI interconnects. The failure scenario of a channel cracking at the interface low-k/TaNTa is treated for the first level. A Finite Element FE model has been developed which shows the impact of the layout and the process on the stress level and interface decohesion probability in this structure. In addition, some general design rules are deduced from these calculations to avert crack propagation in interconnects.

In this paper, we present a highly-performant PMOS transistor architecture featuring a buried strained SiGe layer (stressor) underneath the Si channel and in between the epitaxially grown Si S/D regions. This stressor together with the shallow trench isolation (STI) induces pseudo-biaxial compressive stress in small devices Si channel. A completely different behaviour compared to bulk-Si devices is shown. Transistors featuring a 50nm gate length, a 1.5nm physical gate oxinitride and an active area width of 0.28/spl mu/m demonstrate drive currents up to 740/spl mu/A//spl mu/m with only 48nA//spl mu/m Ioff at a supply voltage of 1.4V. Those results, regarding the oxide thickness, are in the range of the best ever reported. Moreover, this solution provides easy co-integration possibilities between HP, GP and LP (bulk-like or SON: silicon-on-nothing) devices on the same chip.

This paper presents an electrical analysis of mechanical stress induced by shallow trench isolation (STI) on MOSFETs of advanced 0.13 /spl mu/m bulk and silicon-on-insulator (SOI) technologies. By applying external calibrated stress, we present piezoresistive coefficients measurements on these technologies, and we compare small and long transistors electrical responses, evidencing the strong effect of source drain resistance R/sub sd/. Then, using the same approach on short devices with different gate-edge-to-STI distances, we quantitatively evaluate stress profile induced by STI and its mean value under the gate of the devices. Results are discussed to explain differences between bulk and SOI technologies, as well as between nMOS and pMOS. We show that the observed higher pMOS drain current shift is related to the process, and may be explained by doping amorphization and recrystallization effects, and not by a piezoresistive coefficient difference as usually assumed.

Stress induced by thermal expansion mismatch between metal, silicon substrate and dielectrics may affect the integrity of copper interconnects. As a matter of fact, the voids formed by vacancy coalescence beneath vias, are likely to induce opens in the interconnects. With a view to predict the lifetime of copper interconnects, we developed a predictive model of the resistance evolution due to stress induced voiding. This model is validated by experimental investigation of the resistance evolution in time of different types of via chains during isothermal annealing lasting up to 1000 h. This model is able to simulate resistance increase depending on the temperature and geometry. Thus, it is possible to optimize test structures and to evaluate effective acceleration factors.