In this paper, the speed performance, power consumption, and layout area of Neuron MOS transistor circuits are monitored considering the requirements of modern VLSI design. The Neuron MOS transistor is a recently discovered device principle which has a number of input gates that couple capacitively to a floating gate. The floating gate potential controls the current of a transistor channel. This device can be used in logic circuits. A threshold current through the Neuron MOS transistor can be defined that causes a switching of the output of the logic circuits as soon as the channel current surmounts or falls below the specified value. We designed two different multiplier cells, one based on a Neuron MOS inverter, and the other on a Neuron MOS n-MOSFET which is used as one input device of a comparator circuit. Functionality of both cells is proven for data rates up to 50 MHz which represents the first high-speed measurement of a circuit based on this new design principle. A perspective for the upper speed limit found at more than 500 MHz is given by simulation. The new design principle has a layout area reduced by more than a factor of two compared to usual multiplier cells. Moreover, it is shown, that depending on the design chosen, high speed operation leads to considerable power savings. In view of those advantages it is concluded that the principle of threshold logic qualifies for a major breakthrough for packing density improvement of CMOS-based applications.

A powerful method is presented that allows precise determination of the statistical distribution of the input offset voltage of differential pairs which are of prime importance for the accuracy of differential amplifiers. We use a specifically developed test structure with differential pairs arranged in large arrays. A number of layout variants typical for analog applications is realized. Measured data are shown to demonstrate the high performance of the proposed method. On the basis of matching results from this method valuable information is obtained for optimizing analog circuit design.

Based on the neuron MOS transistor principle a multiplier circuit is designed for the first time. High-speed measurements are presented that qualify the principle of threshold logic for a new design principle. This represents a major breakthrough of packing density improvement of CMOS-based logic applications

Statistical intra-die variations of device parameters from a 0.5 μm CMOS process are determined, finding good agreement with the (WL) -1/2 model. It is proven that channel doping variations are responsible. Additionally, systematic proximity-induced parameter deviations due to different field oxide surroundings are found. The resulting variations of inverter delays for different supply voltages and gate areas are determined

The sensitivity of a DRAM sense amplifier, generally consisting of cross-coupled pairs of CMOS transistors is limited by mismatches disturbing the circuit symmetry. The minimum cell signal which is correctly sensed due to process tolerances by a sense amplifier is an important quantity, but extremely difficult to measure. We present such measurements in this paper. On this basis we estimate the cell capacitance necessary for a reliable operation of the DRAM. Moreover we use the sense amplifier on our test structure as a monitor to evaluate the above-mentioned process tolerances. For fast sense amplifier operation and short access times, a large initial sense signal is required. We measure how the minimum sense signal is affected by different sense amplifier trigger pulse shapes and sequences. High density DRAMs with fast access times can only be realized, when all these factors are well-optimized.

Based on a typical 1 6-Mb dynamic-RAM (DRAM) sense amplifier using 0.6-μm design rules, a test structure was designed and the minimum signal voltage for reliable operation of the sense amplifier was determined. The analysis of the measured data provides a monitor for DRAM process control. Variations in gate lengths and capacitances and the influence of the decoupling transistors located between bitlines and sense amplifier were investigated. The local variation in threshold voltage was investigated on a separate test structure on the same wafer. In this way the contribution to the minimum sense signal attributed to mismatches in current gain and parasitic transistor capacitances can be separated. The minimum storage cell capacitance for which correct sensing was possible was determined

A recently developed model for the degradation of Si p-MOS transistors by hot-carrier injection is extended to take into account the detrapping of trapped electrons. Based on their approach, a more reliable and practicable lifetime prediction method for p-MOS transistors is established. A novel expression for the lifetime is derived which is valid in a wider range than the empirical power-law dependence of lifetime on gate current.<>