This work characterizes long channel trigate transistors with respect to the systematic influence of crystal orientation and body doping on performance issues like mobility and Vth adjustment. A fin orientation of 〈1 0 0〉 is found favourable for n-channel, 〈1 1 0〉 for p-channel transistors. Experiment shows that body doping is suitable to taylor Vth, but low doping levels are preferable to reduce Vth variations. The applicability of these long channel results to short-channel transistors down to 20 nm gate length is demonstrated and good performance is obtained.

The trimming of electron beam features is investigated to explore the limits of this scaling technique for the fabrication of nano-scale devices. The semiconductor industry, in particular, needs features below 50 nm, e.g., for extremely small gates for future technology nodes. In addition, sub-lithographic structures are required for other device concepts, such as the fin-type field effect transistor (FinFET). The trimming of very thin layers of calixarene, an organic resist material, as well as an oxide-like resist (hydrogen-silesquioxane) were investigated and extremely small feature sizes, well below 10 nm, were achieved. Resist structures down to 4 nm in width and silicon features of about 8 nm have been successfully fabricated. Different trimming procedures utilizing plasma resist trimming, etching of Tetraethylorthosilicate (TEOS) hard-masks in hydrofluoric acid (HF) and sacrificial oxidation were compared and, for the first time, a comprehensive study of these techniques applied to sub-10 nm-structuring is presented. In summary, results prove the potential of the trimming procedures investigated here, each of which has specific applications.

Tri-gate silicon-oxide-nitride-oxide-silicon (SONOS) NAND string arrays with p+ gate for multi-level high density data flash applications have been fabricated down to 50 nm gate length for the first time. Thick nitride and top oxide layers have been chosen to achieve large threshold voltage shifts of DeltaVth = 6 V at NAND flash compatible times and voltages. In spite of the thick dielectric stack device scalability is not compromised, as shown by simulation for 30 nm gate length. In addition, excellent program inhibit and retention properties as well as tight multi-level threshold voltage distributions have been found

Planar double-gate field effect transistors with asymmetric (p++/n++) independent gates down to 55nm physical gate lengths are successfully fabricated. A fabrication concept, epi-before-bonding, is introduced and demonstrated to be highly successful in achieving ultra-thin and planar Si bodies. Various modes of operations are extensively analyzed and compared to 2D simulations. It is experimentally shown that specific off-current requirements can be fulfilled with conventional poly-Si gates.

High density data flash memories are essentially used in mobile applications. Flash devices have a small form factor, high storage density and low power consumption. For logic applications FinFET type devices are known to have good scalability down to 10nm gate length. This device architecture combined with a trapping layer enables memory cells with feature sizes well below 50nm. To show the scaling potential of SONOS FinFET memories, devices are processed on SOI wafers with fin widths varying from 8nm to 30nm and gate lengths scaled down to 20nm. We discuss three different storage modes of FinFET trapping layer NVM devices: (a) single bit SONOS cell, (b) multilevel SONOS cell and (c) NROM dual bit device. For (a) and (b) program and erase is done with Fowler–Nordheim tunneling and for (c) channel hot electrons are used for programming and hot holes are injected for the erasing of the localized charges. SONOS FinFET memory devices show excellent functionality down to 20nm channel length.

Double-gate transistors are promising successors to conventional bulk MOSFETs, since their gate arrangement limits short channel effects yielding better device performance, even at nanometer size gate lengths. An electron beam lithography process for patterning and aligning the nanometer-size gates of a planar double-gate transistor has been constructed. The gates are structured non self-aligned on both sides of a thin c-Si layer, whereby the first structured gate layer together with the c-Si layer is transferred to a handling wafer using wafer bonding and wafer back-side etching, enabling access to the backside of the c-Si layer. Top and bottom gates have been aligned with 25nm accuracy using topographic marks that are detectable in both exposure steps. Gate lengths of less than 20nm were structured using the hydrogen-silesquioxane (HSQ) resist. With the help of Monte Carlo simulations the optimal electron acceleration voltage was determined to obtain the best resolution possible when patterning top and bottom gates. An intra-proximity correction was introduced for the acceleration voltage used by varying the dose factor of every pattern to be written.

In this paper the limits of trimming techniques are explored. Very thin layers of organic resist material are investigated. Further, extremely small feature sizes down to 8 nm are achieved. Different trimming procedures utilizing resist trimming, HF dip of TEOS hard-mask and sacrificial oxidation are compared.

Charge trapping memory structures with Al2O3 dielectrics as a trapping dielectric are investigated in a metal–Al2O3–oxide–silicon configuration with a metal gate of high work function. The devices show very good write/erase characteristics, endurance, retention and disturb behaviour. At elevated temperature, devices with an Al2O3 trapping layer are found to have better retention properties than devices with a silicon nitride trapping layer.

In this article, ultra-thin-film SOI transistors fabricated by locally recessing the channel regions are presented. SOI MOSFETs with ultra-thin channels offer better scaling properties than bulk transistors due to suppressed short channel effects, reduced parasitic capacitance and easy lateral isolation. The objective of this work was to establish a fabrication scheme for the production of fully depleted (FD) SOI transistors with channel thicknesses of 20 nm and below. An SEM based direct write electron beam lithography was used to pattern structures in the sub 100 nm range. Special emphasis was put on the pattern transfer which is accomplished by high-density plasma etching using hard masks and subsequent resist free silicon patterning with a high density HBr/O"2 plasma. This enabled transistor channels as thin as 1 nm to be produced. Together with standard CMOS production processes NMOS and PMOS transistors with gate lengths down to 48 nm have been fabricated and electrically characterized. In this way recessed channel SOI transistors with channel thicknesses below 10 nm and gate lengths smaller than 50 nm have been achieved for the first time.

FinFETs were the most favourable double gate transistor for the future CMOS device demands due to their improved turn off behaviour caused by better electrostatic channel control, suits especially for battery powered hand held applications. The device was fabricated with an Eltran SOI wafers. Its transfer characteristics reveals its suitability for its application in low power applications.

Ultra-thin-body silicon-on-insulator (UTB-SOI) is one of the most promising candidates for future CMOS technologies with minimum feature sizes below 50 nm. In this paper, we analyse the impact of different combinations of doping profiles and gate sidewall spacer thicknesses on device performance. For this purpose we have simulated fully depleted SOI-MOSFETs with thin undoped silicon bodies using a coupled device and circuit simulation.

In this work, LPCVD deposited TEOS, both densified (DT)/undensified (UDT) and structured/non-structured cases are systematically studied and optimized. We have investigated different oxide type bonding materials for layer transfer applications under various processing conditions. It has been shown that very high bond strengths are achievable with UDT for a short-time and low-temperature annealing. Bonding and device related shortcomings or difficulties are proven to be circumvented. Therefore, we propose the use of wafer bonding with UDT for the integration of layer transfer into the fabrication of microelectronic devices.

We have performed extensive 2D and 3D device simulations to assess the impact of gate and drain voltages, channel doping, discrete impurity effects, and the device dimensions on the electron density accumulation in the corner regions of trigate transistors. For channel doping concentrations higher than 10(18) cm(-3), these 'corner effects' are found to dominate the device behavior. They are most pronounced in the subthreshold regime and significantly reduced in short devices with rounded corners, thin gate oxides, and narrow channels.

This work reports a detailed study of nanoscale ultra-thin (UT) SOI MOSFETs for low power applications. Partially depleted (PD) and fully depleted (FD) NMOS and PMOS devices with a wide range of gate lengths down to 25 nm and silicon thicknesses of 25 nm and 16 nm have been analysed. Gate oxide thicknesses of 2.5 nm and 1.8 nm have also been compared. We demonstrate off current adjustment by channel implantation whereby, together with work function engineering, a suitable solution for multiple Vt SOI CMOS technology could be provided.

Fully-depleted tri-gate oxide-nitride-oxide (ONO) transistor memory cells with very short gate lengths in the range L-G = 30 - 80 nm have been fabricated for the first time. The devices show very good electrical characteristics and have been optimized successfully for high density applications. A NAND-type array organization is proposed and solutions to integration issues are given. In addition, high resolution scanning spreading resistance microscopy has been used to visualize the On-state of a tri-gate memory device.

Fast programmable tri-gate oxide-nitride-oxide (ONO) transistor memory cells with sub-10 nm fin width and gate lengths down to L/sub G/ = 20 nm have been fabricated and successfully operated in multi-level mode for the first time. In spite of thick tunnel oxides required for reliable retention, the devices were optimized for either two level operation with very short program and erase times of t/sub P/ = 20 /spl mu/s and t/sub E/ = 1 ms and threshold voltage shifts of /spl Delta/V/sub th/ /spl sim/ 3 V or for multi-level mode with t/sub PE/ = 2 ms and /spl Delta/V/sub th/ < 4 V. In addition, a simple 6F/sup 2/ NOR array scheme is proposed that meets the large /spl Delta/V/sub th/ shift specific read and write disturb requirements thus allowing for a cost effective high density 3F/sup 2//bit nonvolatile memory for data storage applications.

Dual bit operation of fabricated tri-gate nonvolatile memory devices with aggressively scaled oxide-nitride-oxide (ONO) dielectrics is presented for the first time. Compared to a planar cell, the proposed tri-gate device architecture offers higher readout currents and improved electrostatic gate control of the channel region yielding very good scalability of the devices. We have investigated devices with gate lengths in the range L/sub G/=100-220 nm and we focus on their write-erase, retention, and cycling characteristics.

The leakage mechanisms in fully depleted (FD) SOI transistors with undoped channel are investigated. These devices - contrary to partially depleted devices - show a strong V/sub DS/ dependence of the leakage currents. Energy balance simulations, including band to band tunneling effects and impact ionization, have been carried out. Contrary to drift diffusion calculations, these simulations can account for the experimental data and show that the two effects can be separated. In order to reduce these leakage effects, the design of the drain has to be optimised.

Replacing oxide-nitride-oxide (ONO) dielectrics in charge trapping memories such as SONOS (silicon/ONO/silicon) and NROM (nitrided read only memory) by high-k materials potentially offers improved scaling properties of the devices. In particular, a high dielectric constant of at least one of the three layers allows one to reduce the total equivalent oxide thickness (EOT) thus achieving the same programming electric field as in ONO stacks at reduced voltage. In this study, we evaluate the retention time of charge trapping memories using Al/sub 2/O/sub 3/ as a trapping dielectric and as a control gate dielectric. We find sufficiently large shifts of the threshold voltage allowing for retention times of more than ten years for the Al/sub 2/O/sub 3/ charge trapping memories. High-temperature annealed, polycrystalline layers are found to be more useful than amorphous layers annealed at 400-600/spl deg/C due to better retention time, smaller EOT and flat band shifts and a smaller amount of fixed interface charges.

New device concepts have been introduced to fulfill the demands and scaling requirements of the International Technology Roadmap for Semiconductors (ITRS). This, in turn, increases the demands on the characterization methods, e.g. for the measurement of 2D-carrier profiles, which have to be improved to match. This article reports a comparative study of the electrical and analytical characterization of nanoscaled ultra-thin (UT) n-channel and p-channel SOI transistors. The devices were fabricated on 45 nm SOI with gate lengths as short as 20 nm. The gates were defined by electron-beam lithography and nanoscale dry etching. We use high resolution scanning spreading resistance microscopy (SSRM) to provide reliable information about the carrier profile and effective gate lengths of the devices. The results of these measurements are compared with electrical results and with high resolution TEM.