This paper will describe how Rochester Institute of Technology provides semiconductor manufacturing experiences in a university setting, utilizing lectures, cleanroom tools, cooperative work experience, and collaborative use of appropriate software. For over 40 years these efforts have served as a model for other programs but not enough new programs have been created to close the continuing workforce gaps. It is important to increase the supply of innovative engineers entering the field with "lab to fab" experience. These engineers need to hit the ground running instead of requiring years to acquire the necessary experience. Two software platforms discussed in this paper can be easily used by resource limited programs in conjunction with RIT generated data and expertise to provide key experience levels for students before entering industry.

The heterogeneous integration of semiconductor devices grows in cost as critical device dimensions are pushed to smaller scales. Micro-assembly technologies, such as micro-transfer printing (µTP), offer a solution as they are highly scalable and cost-effective. The µTP approach enables efficient use of growth substrates by smart integration of transferred device “coupons” on receiving “target” substrates. This process allows the fabrication of novel device architectures with reduced critical dimensions and otherwise inaccessible heterojunction configurations, including mixed-dimensional heterostructures (MDH) of III–V semiconductors and two-dimensional (2D) nanomaterials. Here, we describe a process to release III–V device layers from as-grown source substrates before µTP onto 2D materials. Transferrable coupons of lattice-matched InP and InAlAs thin films grown via metal–organic chemical vapor deposition (MOCVD) on InP were fabricated by deposition of a masking oxide and photolithographic patterning, followed by etching to define and release the InP coupons from the sacrificial InAlAs layer. Coupons were micro-transfer-printed onto a range of substrates including silicon, graphene, and monolayer molybdenum disulfide. To elucidate the impact of printing conditions on InP coupon transfer, a design of experiments was conducted to characterize the µTP parameter space in terms of critical pick and print settings. Transfer printing onto low-dimensional monolayer materials can better enable site-specific, high-throughput heterogeneous integration with the high print yields demanded by scalable manufacturing and enable low complexity fabrication for diverse device applications.

Indium tungsten oxide (IWO) has been investigated as an oxide semiconductor candidate for next-generation thin-film transistors (TFTs). Bottom-gate TFTs were fabricated with a 30-nm IWO channel material sputter-deposited with oxygen partial pressure (PO2) ranging from 2.5

The focus of this work is the process integration of Indium Gallium Zinc Oxide (IGZO) transistors as a µLED backplane for row/column addressing. A single pixel is composed of a µLED driven by an arrangement of two transistors and a storage capacitor. The pixels are then arrayed on a glass substrate to support active-matrix control of monochrome and full color (RGB) displays from 1x1cm (50 x 50 pixels) up to 7.6 x 7.6 cm (380 x 380 pixels). Optimization of circuit parameters considering size and scan frequency was modeled using existing TFT and µLED electrical device compact models. New process parameters and procedures were determined for the proper integration of µLEDs in an existing TFT fabrication process. Red, green, and blue µLED devices were fabricated at Tyndall National Institute on native substrates and were transferred to TFT pixels using an X-Display MTP-1003 micro-transfer printer. The performance of individual test cells was assessed using an Agilent B1500, revealing a voltage transfer characteristic indicating the ability to modulate and control µLED current.

Display technologies have continuously evolved since the advent of cathode ray tube (CRT) displays in the early 1900s. Thanks to modern advancements, current display thicknesses are on the order of centimeters and their area has increased 10-fold. Modern flat panel display (FPD) systems consist of a TFT backplane that controls the filtering of a backlight or the modulation of emissive devices such as OLED or microLEDs (µLEDs). MicroLED technology is favored over organic light-emitting diode (OLED) technology due to its higher brightness, energy efficiency, and longer operational lifetime. Additionally, µLEDs offer small pixel sizes, scalability to large screen sizes, and increased durability compared to OLEDs. While both technologies have their strengths and weaknesses, the choice between them depends on specific application requirements and preferences. The primary focus of this work is the process integration of Indium Gallium Zinc Oxide (IGZO) transistors as a µLED backplane for row/column addressing. A single pixel is composed of a µLED driven by an arrangement of two transistors and a storage capacitor. The pixels are then arrayed on a glass substrate to support active-matrix control of monochrome and full color (RGB) displays from 1x1cm (50 x 50 pixels) up to 7.6 x 7.6 cm (380 x 380 pixels). Optimization of circuit parameters considering size and scan frequency was modeled using existing TFT and µLED electrical device compact models. New process parameters and procedures were determined for the proper integration of µLEDs in an existing TFT fabrication process. Red, green, and blue µLED devices were fabricated at Tyndall National Institute on native substrates and were transferred to TFT pixels using an X-Display MTP-1003 micro-transfer printer. The performance of individual test cells was assessed using an Agilent B1500, revealing a voltage transfer characteristic indicating the ability to modulate and control µLED current. Techniques were investigated for the system integration of the active matrix with control circuitry. Figure 1

This work provides an interpretation of donor activation in self-aligned bottom-gate (SA-BG) Indium-Gallium-Zinc Oxide (IGZO) TFTs with ion-implantation of boron (11B+) species as the source/drain treatment. The effect of implant dose on device operation was investigated. Transfer characteristics appeared similar with a boron dose of 1 and 2×1015 cm-2 however, a 45% decrease in max current was observed for devices implanted with a 4×1015 cm-2 dose. Van der Pauw measurements displayed a similar trend; an increase in boron dose resulted in an increase in sheet resistance. A left-shift in transfer characteristics was observed with a greater shift in the 4×1015 cm-2 dose devices, following thermal stability treatments. The existence of two separate boron species is hypothesized, (1) an electrically active donor species involving a relatively small fraction of the total boron concentration and (2) additional boron interstitials and/or other associated defects. A detailed discussion on developed arguments arrived at through analysis of TFT electrical characteristics is presented.

The traditional response to bias-stress treatments is consistent with the Fermi level position during the stress application. Positive-bias stress (PBS) supports trap state filling of electrons, presenting negative interface charge and causing a left-shift and/or distortion in the transfer characteristic. Negative-bias stress (NBS) supports trap state emptying of electrons, appearing as a net positive charge and causing a right-shift and/or distortion in the transfer characteristic. The extent of shifting, distortion, and hysteresis resulting from the bias-stress application depends on the magnitude of the bias-stress voltage and time duration, as well as the post-stress test conditions such as VGS sweep rate and temperature. Hysteresis occurs when the level of trapped charge is not in thermal equilibrium with the temperature and bias conditions, and provides insight into the magnitude of trap states involved in dynamic state changes. This work provides an interpretation of defect and trap state behavior following the application of intensive NBS and negative-bias illumination stress (NBIS). Staggered bottom-gate TFTs were fabricated with a 50 nm IGZO film sandwiched between a 50 nm gate oxide and a 50 nm passivation oxide layer. The working metal was molybdenum for the gate electrode and source/drain contacts. A passivation anneal was done and an alumina capping layer was deposited via ALD to promote electrical stability; full process details are provided in a previous report. Devices were tested with a Keysight B1500 parameter analyzer to establish initial device characteristics, with +20 V PBS and -10 V NBS stress applications for 20 ks having a negligible response. Intensive negative-bias stress testing was then done for 10 ks at either high bias (-20 V NBS) or with the addition of illumination (-10 V NBIS @ 410 nm). The responses to intensive NBS and NBIS applications were both non-traditional and distinctive. Pre- and post-NBS results are shown in Figure 1. ID-VGS transfer characteristics were measured over a VGS down-sweep from 10 V to -5 V at VDS values of 10 V (first) and 0.1 V (second), with a sweep rate of ~ 1 V/s. The measurement order, sweep direction and sweep rate were chosen to maintain consistent non-equilibrium conditions and suppress hysteresis. The intensive NBS shown in Figure 1a induces a significant distortion and spreading to the right, which can be explained by the creation of acceptor-like trap states during stress application. Figure 1b shows a comparison of hysteresis following NBS and subsequent PBS treatments, with the VGS up-sweep immediately followed by a down-sweep. Post-NBS hysteresis shows a separation of approximately 1 V, which translates to an equivalent interface state density difference of 4.3x1011 states/cm2. The separation in transfer characteristics reflects non-homogeneity in trap state formation. The application of +20V PBS following NBS was observed to partially reverse these effects, with hysteresis reduced significantly. The net shift around flatband is minimal, however pronounced distortion remains. Pre- and post-NBIS results are shown in Figure 2. The intensive NBIS shown in Figure 2a induces a significant right-shift of around 6 V, with minimal distortion. While this can also be explained by the creation of acceptor-like traps, the states created in response to NBIS have a slow response (i.e. remain unchanged over VGS sweep) appearing more like fixed charge. Note that this large shift is observed in the hysteresis loop shown in Figure 2b, however once VGS is increased to +10 V the traps remain filled and hysteresis is dramatically reduced. The application of +20 V PBS following NBIS was observed to partially reverse these effects, with a left-shift of approximately -4 V, or to within 2 V of the original pre-NBIS characteristics. The hysteresis loop observed following PBS treatment and relaxation is consistent with the position of the post-NBIS hysteresis measurement (up-sweep) and the final transfer characteristic (down-sweep). Remaining work in defect state characterization will utilize cryogenic measurements for temperature-dependent behavior. TCAD simulation will be used as a resource to model the defect state energy distribution resulting from the application of intensive NBS and NBIS treatments. Figure 1

Self-aligned channel regions in thin-film transistors (TFTs) have advantages in reduced parasitic capacitance and stage delay, and a reduction in overhead real estate. A common method used to fabricate self-aligned a-Si:H TFTs is to utilize a through-glass exposure of photoresist which is blocked by the opaque metal bottom-gate electrode. This process does not require an additional photomask or lithographic alignment, and thus supports low production cost. Sputtered IGZO has been introduced into flat panel display product manufacturing, exhibiting a channel mobility of approximately an order of magnitude higher than a-Si:H. The working source/drain electrodes in IGZO TFTs can be direct metal contact regions to the IGZO, without the need for additional processes such as doping to render the IGZO conductive. Proper metallurgy and annealing processes can provide ohmic behavior with minimal series resistance, however this usually requires several microns of gate-to-source/drain overlap to ensure such behavior. This work provides an interpretation of donor activation in self-aligned bottom-gate IGZO TFTs with ion-implantation of boron (11B+) species as the source/drain treatment. Passivated staggered bottom gate devices were fabricated with a sputtered 50 nm IGZO channel layer. Following standard passivation processes, devices were implanted adjacent to channel regions with boron doses of 1, 2, and 4×1015 cm-2 at an energy of 35 keV. Utilizing this anneal-implant sequence resulted in self-aligned devices with transfer characteristics comparable to non-self-aligned TFTs. Upon comparing linear mode device characteristics (Vds = 0.1 V) between the different treatments, a dose dependence was observed. Transfer characteristics appeared similar with a boron dose of 1 and 2×1015 cm-2 however, a 45% decrease in max current was observed for devices implanted with a 4×1015 cm-2 dose. From Van der Pauw measurements, a similar trend was observed; an increase in boron dose resulted in an increase in sheet resistance. A left shift in transfer characteristics was observed following thermal stress at 175 °C which is hypothesized to be the result of an interstitial boron species that remains mobile and provides a relatively low dose throughout the channel during and after thermal stress. An increased boron dose is hypothesized to result in a greater concentration of interstitial boron resulting in a greater degree of transfer characteristic shifting following thermal stress. An alternative hypothesis involves the possibility of hydrogen contamination during the implant process. The results of the investigation on the source of instability will be presented. Figure 1

The invention of portable electronic devices had a huge impact on the growing interest in flat panel displays. Since the first report in 2004 on amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors (TFTs), many companies have become interested in this material. The main advantage of a-IGZO over conventional amorphous silicon TFTs is its steep subthreshold, low off state current, and high channel mobility. However, the demand for larger displays with higher resolution and refresh rates is driving the demand for TFTs with higher performance, while avoiding the cost and complexity associated with low temperature polycrystalline silicon. There is an increased focus on alternative amorphous oxide semiconductors for use as TFT channel materials, due to the success of a-IGZO. The focus of this study is an investigation on Indium-Tin-Gallium-Oxide (ITGO) TFTs. Unpassivated bottom-gate devices were fabricated with a 30nm a-ITGO film, sputter deposited with 1% and 10% oxygen gas ambient, followed by a 2 hour anneal at 300oC in oxygen. Devices fabricated with PO2 = 1% resulted in a highly conductive channel. Devices with PO2 = 10% displayed semiconducting behavior and a shallow subthreshold. This trend held for all device dimensions tested; lengths of 24µm, 12µm, and 6µm with a width of 24µm. Compared to a-IGZO devices with a length of 4µm, ITGO devices with a length of 12µm exhibit an equivalent current drive, implying a 3 to 4 times improvement in mobility. Following aging in room ambient for multiple days, a-ITGO devices displayed improved yet left-shifted transfer characteristics. In unpassivated a-IGZO devices, similar behavior can also be observed and is attributed to an inhomogeneous trap distribution across the channel. As the exposed channel reacts with room air, oxygen vacancies are filled resulting in a more homogeneous trap distribution. A radial variation of device performance from the center of the wafer to the edge was also observed. When measuring devices towards the edge of the wafer a considerable left shift in transfer characteristics was observed. This variation in device performance is believed to be attributed to non-uniformities in the as deposited ITGO film and will be related to material optical parameters. Figure 1

There is wide variation in the understanding of the interaction and/or independence of channel mobility and charge trapping in IGZO TFTs. A new interpretation of transport behavior proposes an intrinsic channel mobility with distinctive temperature dependence. Bottom-gate TFTs were fabricated with a 50 nm IGZO film sandwiched between a 50 nm gate oxide and a 50 nm passivation oxide layer. The working metal was molybdenum for the gate electrode and source/drain contacts. A passivation anneal was done and a capping layer was added to promote electrical stability; full process details are provided in a previous report. Devices were tested using a Lakeshore cryogenic probe station, with transfer characteristic measurements taken from room temperature to below 100 K. Electrical measurements made on long-channel devices (L = 12 µm) has revealed temperature-dependent behavior that is not explained by existing TCAD models employed for defect states and carrier mobility. An IGZO TFT device model has been recently developed using Silvaco Atlas, which accounts for the role of donor-like oxygen vacancy defects, acceptor-like BTS, acceptor-like interface traps, and a temperature-dependent intrinsic channel mobility. The model demonstrates a remarkable match to transfer characteristics measured at T = 150 K to room temperature. The temperature-dependent mobility follows a power-law relationship resembling behavior consistent with ionized defect scattering; the source of which is proposed. Details of the material and device model, and associated defect distribution parameters will be presented. Figure 1

The focus of this study is an investigation on Indium-Tin-Gallium-Oxide (ITGO) TFTs. Unpassivated bottom-gate devices werefabricated with a sputter-deposited 30nm a-ITGO film with 1% and10% oxygen gas ambient, followed by a 1 or 2 hour anneal at 300oCin oxygen. Devices fabricated with PO2 = 1% resulted in a highlyconductive channel, whereas devices with PO2 = 10% displayedsemiconducting behavior and a shallow subthreshold. Followingaging in room ambient for multiple days, devices displayed left-shifted transfer characteristics with steep subthreshold. It ishypothesized that the unpassivated back-channel attains a morehomogeneous trap distribution. The ITGO devices demonstrate aneffective channel mobility approximately 2.5 times higher thanIGZO TFTs. Radial variation in device performance can beattributed to non-uniformities in the as-deposited ITGO film, with acorrelation to the distribution in optical constants across the wafer.

A device model developed for the on-state operation of accumulation-mode IGZO TFTs is presented as an adaptation of a Level 2 SPICE (L2S) model. The model accounts for the ionization and deionization of acceptor-like band-tail states (BTS), as controlled by both the gate and drain bias conditions. I-D - V-DS output characteristics are well represented by the device model which includes the physical channel length and width, gate dielectric thickness, and seven operational parameters. Along with selected traditional L2S parameters, the introduced BTS parameters accurately reflect the level of free electron charge and associated current in triode and saturation modes. Model parameters were extracted using regression analysis on output characteristics with fine gate voltage increments. The device model accurately represents long-channel and scaled devices with bottom-gate and double-gate electrode configurations. The physical correlation of the model to device operation is demonstrated through comparisons with measured characteristics and TCAD simulation.

Indium gallium zinc oxide (IGZO) has been considered a potential replacement for hydrogenated amorphous silicon in TFT applications due to process compatibility and an order of magnitude improvement in electron channel mobility. However the mechanisms responsible for instability under bias-stress remain an active research topic. Silicon dioxide serving as the gate dielectric and back-channel passivation layer in bottom-gate IGZO TFTs results in high quality interfaces. Applied bias-stress conditions demonstrate a voltage shift that can be attributed to ionization and/or alteration of oxygen-related defects at these IGZO/SiO2interfaces. Bottom-gate IGZO TFTs with SiO2 gate dielectric and passivation layers were fabricated and tested under rigorous positive bias-stress (PBS) and negative bias-stress (NBS) conditions. The devices demonstrate good stability under PBS (t > 104 s), with minor distortion in the subthreshold region and a slight characteristic left-shift from an initial pre-stress state. This PBS-shift is attributed to a change in the energy distribution of defect states at the front-channel interface. During NBS the devices exhibited a significant left-shift (ΔV ~ 1-2 V), which is attributed to the transformation of neutral oxygen vacancies to ionized donor states at the back-channel interface. This transformation appears to improve the electrical homogeneity of the back-channel interface, inferred by a suppression of DIBL-like behavior. The NBS-shift was found to be reversible over long recovery times at room temperature. The recovery time was dramatically reduced when samples were subjected to cryogenic temperature (77 K), which represents an accelerated return to the pre-stress condition. TCAD simulation provides additional support to the interpretation of bias-induced stress on IGZO TFTs.

The classic bottom-gate IGZO TFT structure requires a passivation layer application over the back-channel for stability and process integration. However, the passivation material deposition process usually degrades the interface quality and presents defect states at the back-channel interface which are difficult to compensate by a controlling gate electrode positioned on the opposite side of the semiconductor. A top-gate configuration takes advantage of a superior back-channel interface between the substrate and the sputtered IGZO film. The gate dielectric must be deposited on the IGZO which presents an inferior interface, however the influence of defect states can be reduced by annealing in an oxidizing ambient prior to the gate electrode deposition. As positioned directly above the inferior interface, there is an improvement in the ability of the gate potential to control the device operation in the presence of remaining defect states. This work presents an investigation on TFTs which have been fabricated with very similar process flows with the exception of the placement of the gate electrode. Bottom-gate TFTs with back-channel passivation that demonstrate good performance and resistance to aging have been realized, however bias-stress stability continues to remain a challenge. Top-gate TFTs have demonstrated improvement in the uniformity of device operation as well as bias-stress stability, and have the potential to offer an advantage in off-state performance (see fig. 1). Double-gate TFTs take further advantage of improved electrostatics, but present additional challenges in process integration. Results from all three gate electrode configurations will be compared. Device testing performed over a temperature range from 10 K to 400 K allows a comprehensive assessment of transport behavior (see fig. 2), with results used to refine a material and device model for TCAD simulation. Figure 1

This work presents an investigation on TFTs which have been fabricated with very similar process flows with the exception of the placement of the gate electrode. Bottom-gate TFTs with back-channel passivation that demonstrate good performance and resistance to aging have been realized, however bias-stress stability continues to remain a challenge. Top-gate TFTs have demonstrated improvement in the uniformity of device operation as well as bias-stress stability, and have the potential to offer an advantage in off-state performance. Double-gate TFTs take further advantage of improved electrostatics, but present additional challenges in process integration. Device operation and response to applied bias-stress of all three gate electrode configurations will be compared, with reference to TCAD simulations that utilize common bulk and interface defect models. Electrical measurements and TCAD simulations are also used to develop a hypothesis on the origin of non-ideal behavior observed on scaled devices, which can be addressed by appropriate gate electrode option.