A device model developed for the on-state operation of accumulation-mode IGZO TFTs is presented as an adaptation of a Level 2 SPICE (L2S) model. The model accounts for the ionization and deionization of acceptor-like band-tail states (BTS), as controlled by both the gate and drain bias conditions. I-D - V-DS output characteristics are well represented by the device model which includes the physical channel length and width, gate dielectric thickness, and seven operational parameters. Along with selected traditional L2S parameters, the introduced BTS parameters accurately reflect the level of free electron charge and associated current in triode and saturation modes. Model parameters were extracted using regression analysis on output characteristics with fine gate voltage increments. The device model accurately represents long-channel and scaled devices with bottom-gate and double-gate electrode configurations. The physical correlation of the model to device operation is demonstrated through comparisons with measured characteristics and TCAD simulation.

Flash-lamp annealing (FLA) has been investigated for crystallization of patterned amorphous silicon (a-Si) in the fabrication of NMOS and PMOS Thin-Film Transistors (TFTs) on display glass. Samples were exposed with a xenon flash irradiance of similar to 30 kW/cm(2) and pulse duration of 200 mu s, with bolometer measurements showing an integrated energy of similar to 6 J/cm(2). Non-self-aligned TFTs fabricated from the resulting polycrystalline silicon demonstrated electron and hole channel mobility values in excess of 300 cm(2)/(Vs) and 100 cm(2)/(Vs), respectively. According to the authors' knowledge, this is the first report of CMOS TFTs demonstrated using the FLA technique. (c) The Author(s) 2017. Published by ECS.

Indium gallium zinc oxide (IGZO) has been considered a potential replacement for hydrogenated amorphous silicon in TFT applications due to process compatibility and an order of magnitude improvement in electron channel mobility. However the mechanisms responsible for instability under bias-stress remain an active research topic. Silicon dioxide serving as the gate dielectric and back-channel passivation layer in bottom-gate IGZO TFTs results in high quality interfaces. Applied bias-stress conditions demonstrate a voltage shift that can be attributed to ionization and/or alteration of oxygen-related defects at these IGZO/SiO2interfaces. Bottom-gate IGZO TFTs with SiO2 gate dielectric and passivation layers were fabricated and tested under rigorous positive bias-stress (PBS) and negative bias-stress (NBS) conditions. The devices demonstrate good stability under PBS (t > 104 s), with minor distortion in the subthreshold region and a slight characteristic left-shift from an initial pre-stress state. This PBS-shift is attributed to a change in the energy distribution of defect states at the front-channel interface. During NBS the devices exhibited a significant left-shift (ΔV ~ 1-2 V), which is attributed to the transformation of neutral oxygen vacancies to ionized donor states at the back-channel interface. This transformation appears to improve the electrical homogeneity of the back-channel interface, inferred by a suppression of DIBL-like behavior. The NBS-shift was found to be reversible over long recovery times at room temperature. The recovery time was dramatically reduced when samples were subjected to cryogenic temperature (77 K), which represents an accelerated return to the pre-stress condition. TCAD simulation provides additional support to the interpretation of bias-induced stress on IGZO TFTs.

The classic bottom-gate IGZO TFT structure requires a passivation layer application over the back-channel for stability and process integration. However, the passivation material deposition process usually degrades the interface quality and presents defect states at the back-channel interface which are difficult to compensate by a controlling gate electrode positioned on the opposite side of the semiconductor. A top-gate configuration takes advantage of a superior back-channel interface between the substrate and the sputtered IGZO film. The gate dielectric must be deposited on the IGZO which presents an inferior interface, however the influence of defect states can be reduced by annealing in an oxidizing ambient prior to the gate electrode deposition. As positioned directly above the inferior interface, there is an improvement in the ability of the gate potential to control the device operation in the presence of remaining defect states. This work presents an investigation on TFTs which have been fabricated with very similar process flows with the exception of the placement of the gate electrode. Bottom-gate TFTs with back-channel passivation that demonstrate good performance and resistance to aging have been realized, however bias-stress stability continues to remain a challenge. Top-gate TFTs have demonstrated improvement in the uniformity of device operation as well as bias-stress stability, and have the potential to offer an advantage in off-state performance (see fig. 1). Double-gate TFTs take further advantage of improved electrostatics, but present additional challenges in process integration. Results from all three gate electrode configurations will be compared. Device testing performed over a temperature range from 10 K to 400 K allows a comprehensive assessment of transport behavior (see fig. 2), with results used to refine a material and device model for TCAD simulation. Figure 1

This work presents an investigation on TFTs which have been fabricated with very similar process flows with the exception of the placement of the gate electrode. Bottom-gate TFTs with back-channel passivation that demonstrate good performance and resistance to aging have been realized, however bias-stress stability continues to remain a challenge. Top-gate TFTs have demonstrated improvement in the uniformity of device operation as well as bias-stress stability, and have the potential to offer an advantage in off-state performance. Double-gate TFTs take further advantage of improved electrostatics, but present additional challenges in process integration. Device operation and response to applied bias-stress of all three gate electrode configurations will be compared, with reference to TCAD simulations that utilize common bulk and interface defect models. Electrical measurements and TCAD simulations are also used to develop a hypothesis on the origin of non-ideal behavior observed on scaled devices, which can be addressed by appropriate gate electrode option.

A study of the influence of back-channel alumina passivation on the operation of bottom-gate IGZO TFTs is presented. TFTs without any passivation material deposited typically exhibit best-case initial results. Regardless a passivation layer is required for device stability and process integration. The impact of passivation using alumina deposited via electron beam evaporation and atomic layer deposition (ALD) has been investigated. A decrease in subthreshold slope and channel mobility on certain treatment combinations is attributed to an inferior IGZO/alumina back-channel interface. A two-step passivation process has been developed which offers back-channel protection during device fabrication, and remains compatible with an oxidizing ambient anneal. Modifications in the passivation and annealing procedures and process integration details have resulted in a marked improvement in the performance of alumina passivated devices, with demonstrated resistance to aging.

This work investigates the quality of back-channel passivation applied to sputter-deposited IGZO bottom-gate TFTs. Passivation materials investigated were alumina, silicon dioxide, and B-staged bisbenzocyclobutene-based (BCB) resins. Sputtered quartz and PECVD (TEOS) SiO2 rendered the IGZO material highly conductive (ρ < 0.01 Ω·cm), with subsequent annealing in oxidizing ambient unable to restore a high-resistivity state. Appropriate channel resistivity was restored on devices passivated with electron-beam evaporated alumina and spin-coated BCB when followed by annealing in air. Alumina passivated devices demonstrated improved stability; however slight distortions in measured I-V and C-V characteristics were observed. TCAD simulation was used to develop an IGZO material/device model, with results indicating the significant presence of oxygen-vacancy (OV) interface traps and negative fixed charge remaining at the back-channel.

Flash-lamp annealing (FLA) has been investigated for the crystallization of a 60 nm amorphous silicon (a-Si) layer deposited by PECVD on display glass. Input factors to the FLA system included lamp intensity and pulse duration. Conditions required for crystallization included use of a 100 nm SiO 2 capping layer, and substrate heating resulting in a surface temperature ∼ 460 °C. An irradiance threshold of ∼ 20 kW/cm 2 was established, with successful crystallization achieved at a radiant exposure of 5 J/cm 2 , as verified using variable angle spectroscopic ellipsometry (VASE) and Raman spectroscopy. Nickel-enhanced crystallization (NEC) using FLA was also investigated, with results suggesting an increase in crystalline volume. Different combinations of furnace annealing and FLA were studied for crystallization and activation of samples implanted with boron and phosphorus. Boron activation demonstrated a favorable response to FLA, achieving a resistivity ρ < 0.01 Ω•cm. Phosphorus activation by FLA resulted in a resistivity ρ ∼ 0.03 Ω•cm.

There has been significant progress in advancing the performance of IGZO TFTs; however device stability still remains a challenge. While traditional materials and techniques used for silicon-based TFTs may not be applicable, the influence of defect states can be reduced by annealing. The interpretation of non-ideal current-voltage (I-V) characteristics is not always unambiguous due to issues that may be related to carrier injection. Capacitance-voltage (C-V) analysis provides complementary information that is valuable in separating the influence of material and interface defects from other factors that influence transistor operation. In this work, bottom-gate, top-contact TFT structures and interdigitated capacitors fabricated using sputtered IGZO have been investigated. Interdigitated capacitors, unlike one-dimensional capacitors, are much more representative of the actual TFT structure; specifically the channel region. Annealing was performed at 300 - 400 °C in O2, N2and air ambient conditions. Silicon dioxide, aluminum oxide, and B-staged bisbenzocyclobutene-based (BCB) resins were applied as materials for back-channel passivation. Analytical measurements and both I-V and C-V results were used to refine a material model developed for TCAD device simulation [1]. The correlation between I-V and C-V characteristics will be presented. [1] T. C. Fung, C. S. Chuang, C. Chen, K. Abe, R. Cottle, M. Townsend, et al., "Two-dimensional numerical simulation of radio frequency sputter amorphous In-Ga-Zn-O thin-film transistors," Journal of Applied Physics, vol. 106, p. 084511, 2009.

Capacitance-voltage (C-V) analysis is a valuable tool in separating the influence of material and interface defects from other factors that influence transistor operation. Thin-film transistors and interdigitated capacitors fabricated using sputtered IGZO have been studied to enhance the interpretation of defect states. Interdigitated capacitors are representative of the TFT channel region, and large-area designs provide a high capacitance swing from depletion to accumulation. Alumina was applied for back channel passivation, with annealing performed at 400 °C in oxidizing ambient conditions. Both I-V and C-V results were used with TCAD device simulation to develop a refined material and device model.

Flash-lamp annealing (FLA) is an alternative technique for crystallization of amorphous silicon which can be scaled to large substrates. A process using FLA may have significantly reduced process complexity and time; however published results that demonstrate potential for use in flat panel displays have been limited [1]. This work investigates FLA in combination with metal-induced crystallization (MIC). The FLA system used in this work is a NovaCentrix PulseForge 3300, which anneals the material using a series of short but intense bursts of broad spectrum light from xenon flash lamps. High peak power over microseconds time scale can provide control over the depth of heating to avoid damage when processing on substrates such as glass or plastic. Input factors to the FLA system included lamp intensity, pulse width, number of pulses and repetition rate. Since samples are not in thermal equilibrium during FLA, power/time/flash-count combinations that deliver the same energy produce very different results. Additional factors included use of an anti-reflective SiO 2 layer, and substrate heating (steady-state). Performing FLA on samples with trace amounts of nickel has demonstrated effective crystallization with single-pulse exposures delivering energy of ~ 5 J/cm 2 . Experiments which investigate the influence of both MIC and FLA process parameters on the material properties and electrical characteristics of TFTs will be presented. [1] S. Saxena, D. C. Kim, J. H. Park, and J. Jang, "Polycrystalline silicon thin-film transistor using Xe flash-lamp annealing," IEEE Electron Device Letters, vol. 31, pp. 1242-1244, 2010

Annealing processes were investigated on Indium-Gallium-Zinc-Oxide (IGZO) thin-film transistors (TFTs). Molybdenum and aluminum were used as contact metals which defined the working source/drain electrodes. Annealing was performed either pre-metal or post-metal deposition, in various gas ambients including air, oxygen, nitrogen, forming gas (5% H2 in N2) and vacuum. Pre-metal annealing in air ambient resulted in similar I-V characteristics on Mo-contact and Al-contact devices. A post-metal anneal for Mo-contact devices resulted in higher on-state current and steeper subthreshold slope, whereas the Al-contact devices experienced severe degradation suggesting the formation of an AlOx interface layer. A post-metal anneal at 400 °C in N2 followed by an air ambient ramp-down yielded Mo-contact devices with SS ~ 200 mV/dec, channel mobility µsat ~ 8.5 cm2/V∙s, and improved stability over other anneal conditions.

The influence of annealing ambient conditions and deposited passivation materials on indium-gallium-zinc-oxide (IGZO) thin-film transistor (TFT) performance is investigated. Results from annealing experiments confirm that a nominal exposure to oxidizing ambient conditions is required, which is a function of temperature, time and gas environment. Nitrogen anneal with a controlled air ramp-down provided the best performance devices with a mobility (μsat) of 11-13 cm2/V-s and subthreshold slope (SS) of 135-200 mV/dec, with some hysteresis. Plasma-deposited passivation materials including sputtered quartz and PECVD SiO2demonstrated a significant increase in material conductivity, which was not significantly reversible by an oxidizing ambient anneal. E-beam evaporated Al2O3 passivated devices that were annealed in air at 400 °C demonstrated improved stability over time and suppressed hysteresis in comparison to unpassivated devices. Devices which were passivated with B-staged bisbenzocyclobutene-based (BCB) resins and annealed in air at 250 °C also exhibited suppressed hysteresis.

This work presents a study on the activation behavior of high-dose (φ > 10 15 cm −2 ) boron and phosphorus implants for low resistance source and drain regions for thin-film transistors (TFTs) fabricated using solid-phase crystallization (SPC) of amorphous silicon. Process variables include factors associated with ion implant and annealing conditions, as well as the SPC and implant process arrangement. Four-point probe sheet resistance (Rs) measurements were used as a comprehensive assessment of the electrical properties. Results have identified similarities and differences in activation behavior that can influence process integration strategies considering both the SPC approach and TFT fabrication.