Apart from traditional test and measurement systems where clock synchronization is required, new emerging application areas like SmartGrids and 4G cellular mobile backhaul networks present strong timing constraints in terms of precise time synchronization. Precision Time Protocol (PTP), as defined in IEEE 1588 standard, offers sub-microsecond synchronization using conventional Ethernet networks. Thus, its acceptance is heavily increasing. However, the protocol performance was reduced in large cascaded networks with varying latencies. This drawback was later softened by the second version of the standard with the introduction of the Transparent Clock (TC) device. In this paper, a general overview of PTPv2 and the utilization of TCs is outlined. The main contribution is a new TC architecture for a FPGA-based network device that benefits from reconfigurable devices flexibility.

The matrix converter can be used in a wide range of applications. Nevertheless, it does not yet represent a sufficiently mature option for industrialization. In order to resolve this problem, this paper examines the hardware of the matrix converter and identifies all the circuits that should be included in this. It also quantifies the operating conditions and provides practical guidelines for the step-by-step design of a matrix converter. These considerations are validated with experimental results. In this way, it can be said that this paper represents a step forward toward the development of reliable matrix converters for real applications.

The matrix converter (MC) presents a promising topology that needs to overcome certain barriers (complexity of the modulation and control techniques, protection systems, etc.) in order to gain a foothold in the industry. Traditionally, the MC has been controlled by means of a DSP, together with a field-programmable gate array (FPGA). The sole aim of the latter is to perform the safe commutation of the converter. This involves a waste of resources, as the excellent features of the FPGA are infrautilized by the control system. This paper deals with the implementation of the double-sided space vector modulation (DS SVM), commutation, reference-frame changes, and protection of the MC through a series of hardware blocks (cores) integrally implemented in an FPGA. The designed cores are technology-independent descriptions, which means that the developed design can be used in the FPGAs of any manufacturer. Moreover, the proposed design, which has been validated experimentally, has obviated the need to use a DSP. Likewise, given that all the processing capabilities have been integrated in a single chip, it can be said that an FPGA-based system on a programmable chip (SoPC) has been designed. Due to the computational capacity of the developed cores, processing time is reduced to the order of nanoseconds. This allows a response in real time and very high modulation frequencies can be attained. Moreover, these cores operate independently, and simultaneously, therefore obviating the need for sequential control and its resulting latencies and leading to an increase in the safety of the MC.

The matrix converter (MC) presents a promising topology that will have to overcome certain barriers (protection systems, durability, the development of converters for real applications, etc.) in order to gain a foothold in the industry. In some applications, where continuous operation must be insured in the case of a system failure, improved reliability of the converter is of particular importance. In this sense, this article focuses on the study of a fault tolerant MC. The fault tolerance of a converter is characterized by its total or partial response in the case of a breakage of any of its components. Taking into consideration that virtually no work has been done on fault tolerant MCs, this paper describes the most important studies in this area. Moreover, a new method is proposed for detecting the breakage of MC semiconductors. Likewise, a new variation of SVM modulation with failure tolerance capacity is presented. This guarantees the continuous operation of the converter and the pseudo-optimum control of a PMSM. This paper also proposes a novel MC topology, which allows the flexible reconfiguration of this converter, when one or several of its semiconductors are damaged. In this way, the MC can continue operating at 100% of its performance without having to double its resources. In this way, it can be said that the solution described in this article represents a step forward towards the development of reliable matrix converters for real applications.

This article deals with the implementation of the commutation and protection of the matrix converter (MC) via some hardware blocks (cores) implemented in an FPGA. Thanks to the computational capacity of the cores, processing time is reduced. This allows a response in real time improving the safety of the MC.

Recently, Matrix Converter (MC) has attracted the interest of the scientific community. Due to the complexity of its control, simulation of this converter is a time consuming task. In this work, an FPGA based MC model is presented, allowing the simulation of a detailed MC in real-time.

This paper presents an entire FPGA implementation of a modulation technique for matrix converter known as Double-Sided Generalized Scalar Pulse Width Modulation. The main advantage of this technique is the possibility to emulate the behaviour of many modulation techniques, including the wellknown Space Vector Modulation. Due to the absence of complex algebraic and trigonometric operations in the generalized modulation technique, it is possible to implement the entire control system of the matrix converter in a single FPGA chip. Simulations and experimental results show the effectiveness of the implementation. (6 pages)

FPGAk (Field Programmable Gate Array), hardware funtzionalitate konplexuak egikari ditzaketen gailu birkonfiguragarriak dira. Azken urteotan, izugarri garatu dira eta ASICen (Application Specific Integrated Circuit) eta prozesagailuetan oinarrituriko konponbideen abantaila garrantzitsuenak biltzen dituzte. Horrela, sistema digital oso bat inplementatzeko adinako ahalmena daukate. Ondorioz, gailu horien erabilera gero eta zabalagoa da, eta DSPen (Digital Signal Processor) edo mikroprozesagailuen ordez erabiltzen ari dira aplikazio askotan. Gainera, FPGA hornitzaileek goi mailako software erremintak eskainita, erraztu egiten dute lana, beti ere teknologia horrek eskaintzen dituen abantailak aplikazio-ingurune berrietara zabaltzeko helburua dagoelarik ikusmiran. Zabalkuntza horren erakusgarri da, potentzia-bihurgailuen kontrol-sistemak inplementatzeko gero eta baliabide erabiliagoak izatea. Horrekin batera, FPGA batean inplementatu den Bihurgailu Matrizial (MC, Matrix Converter) baten kontrol-sistema aurkezten da.

The matrix converter (MC) arouses a growing interest because it provides many advantages. On the other hand, the association of these converters in parallel makes the operation of the system operation more reliable and offers the possibility of creating electrical micro-grids. This article presents a parallel association of MCs by droop parallelization technique, which allows the control of several parallel MCs without needing communication between them. This configuration also offers the possibility to achieve an even load sharing. The obtained results demonstrate the feasibility of this technique.

The matrix converter (MC) presents a promising topology that needs to overcome certain barriers (complexity of the modulation and control techniques, protection systems, etc.) in order to gain a foothold in the industry. This article deals with the implementation of the DS SVM vector modulation, commutation and protection of the MC through a series of hardware blocks (cores) integrally implemented in an FPGA. Likewise, given that all the processing capabilities have been integrated in a single chip, it can be said that an FPGA-based System on a Chip (SoC) has been designed.

The topology of the Matrix Converter (MC) is promising because of its intrinsic advantages. Nevertheless, the MC is not as robust as other converters and therefore, under certain fault situations, the converter may be damaged. Certain applications of the MC, such as aeronautics, submarines, etc. require fault tolerant strategies that guarantee the continuous operation of the system under fault conditions. This article examines, in the first place, the behavior of the MC when it is protected by the clamp circuit and one of its switches is in open circuit due to a fault. In order to improve the fault tolerance of the MC, three SVM modulation variations are proposed. On the one hand, two of these variations guarantee the safety of the converter, but the THD of the synthesized voltages and currents is high. On the other hand, the third strategy enhances these and ensures the control of a PMSM in a fault situation.

This paper presents a particular modulation technique based on the generalized scalar pulse width modulation strategy for matrix converters. The objective of this solution is producing identical duty cycles and double-sided switching pattern that the well-known space vector modulation technique without the high memory requirements and the complex trigonometric operations of the last. Both the space vector and the proposed modulation techniques are simulated in a permanent magnet synchronous machine fed by a matrix converter. Its performances are compared with respect to total harmonic distortion (THD), execution times, number of operations and memory requirements. A wide range of simulations are carried out to verify the advantages of the proposed modulation technique when compared with the space vector modulator.