Thin SiGe-channel confinement is found to provide significant control of the short channel effects typically associated with nonbandedge gate electrodes, in an analogous manner to ultrathin-body approaches. Gate workfunction requirements for thin-SiGe-channel p-type field effect transistors are therefore relaxed substantially more than what is expected from a simple observation of the difference between gate and channel work-functions. In particular, thin-SiGe channels are shown to enable cost-effective high-performance bulk CMOS technologies with a single gate workfunction near the conduction bandedge.

As processes are being defined and transistor architectures are being selected for the 45 nm node, the International Technology Roadmap for Semiconductors (ITRS) provides a worthwhile reference for comparing options. In this paper, we discuss those parameters of the ITRS which are related to transistor junctions, from the viewpoint of one selecting a transistor design. Any selection involves tradeoffs, so by addressing how much leeway is expected for the different targets, those selections can be simplified. Along the way, we highlight some interesting contrasts, and present some unique approaches for reaching the targets

We present a low cost, single metal gate/high-k gate stack integration, which provides a very high performing NMOS coupled with a counter-doped PMOS for a 45mn low power (LP) CMOS technology. Inversion To,. (T-inv)values of 16 angstrom/18 angstrom (NMOS/PMOS) result in gate leakage current densities of 0.1/0.01 A/cm(2) and enable self-heated drive currents of 850/325 mu A/mu m at InA/mu m off-state leakage and V-dd=1V (900/340 mu A/mu m non-self-heated). Additionally, the NMOS drive current of 1550uA/[mu m (1650 mu A/mu m non-self-heated) at an I-off= 100nA/mu m and V-dd=1.2V is the highest reported for a hafnium-based high-k gate stack. The approach is compatible with a dual-gate oxide (DGO) module for I/O devices and allows optimization for performance and power typically only possible in triple gate oxide architectures. (1).

Raised source/drain (S/D) or raised extension in fully-depleted-SOI (FDSOI) is necessary to boost saturation current, because of increased resistance from the very thin film. We demonstrate that the choice of raising the extension versus the S/D, will depend upon the maximum achievable mobility in the structure at a 60 nm physical gate length. We also study the effects of minimum BEOL via spacing on performance, and its consequence on choosing a raised extension or S/D.

It is well accepted that one of the key parasitic resistances in ULSI transistors is the contact resistance between the silicide and the doped source/drain. In this paper, we investigate the individual components of this parameter. We show that the contact length is already a contributor at the 90 and 65nm nodes. Changing active doping in the Si via dose/energy modulations can reduce contact resistance in a low temperature flow, but not sufficiently to match results at high temperature. The largest knob is barrier height, leading some to consider moving to 2 different materials for contact to N+ and P+ regions (to replace a single silicide) which, although more complicated for processing may provide significant reductions in resistance. Using modifications to standard test structures and evaluation techniques, it becomes feasible to isolate the individual components of resistance, and to make significant progress in reducing this resistance.