We propose and demonstrate, with hardware, the first experimental technique to measure a vertical component of FinFET source resistance. Forward bias is applied to the well-to-source p-n junction, and the forward voltage at constant current density, ${V}_{{\text {fb}}}$ , is measured as a function of source-current, ${I}_{\text {ds}}$ . The source-current, ${I}_{\text {ds}}$ , is varied by variation of ${V}_{\text {gs}}$ , and an effective vertical resistance is calculated, ${R}_{\text {ve}} =$ dV fb / dI ds . Significant self-heating effects of the p-n junction are observed, and we demonstrate a technique to correct ${V}_{\text {fb}}$ for the local rise in temperature. We find that our technique gives well-behaved results for vertical source resistance. Quantitative ${R}_{\text {ve}}$ values are found to be consistent with technology characterization of (linear region) total device resistance.

We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride materials that allows superior process integration for scaling while simplifying the SRAM cross-couple wiring. We show that the key feature to avoid both gate-contact (CB) to source-drain local interconnect (LI) shorts and the LI-contact (CA) to gate shorts is the shape of the LI cap. A trapezoid-shaped oxide (SiO 2 ) LI cap with an appropriate taper angle eliminates shorting between the contacts in the gate and source-drain region. We further demonstrate that this oxide LI cap is fully compatible with Cobalt (Co) metallization with a novel selective tungsten (W) growth process. Additionally, this process enables the SRAM cross-couple (XC) in the same metallization level, eliminating the need for an upper level wiring and greatly simplifying routing in the SRAM cell.

Raman scattering studies were carried out on epi Si/Si 1-x Ge x ( x = 0.1 to 0.3) heterostructures consisting of a thin Si cap layer (100 - 400 Å), a grade-down Si 1-x Ge x layer, a constant Si 1-x Ge x , buffer layer and a grade-up graded Si 1-x Ge x layer on (100) oriented Si substrates. Different Ge composition, Si 1-x Ge x layer thicknesses and thermal treatment were used to achieve different relaxation in the Si 1-x Ge x layers. It has been revealed that, to a very good approximation, the absolute strains in the cap Si and constant Si 1-x Ge x layers follow a simple sum-rule that is imposed by the lattice mismatch between unstrained Si and completely relaxed Si 1-x Ge x . This sum rule can be used to determine the Ge composition and stresses in both cap Si and constant Si 1-x Ge x layers. Excellent agreement was found between the theoretical curve obtained with LO phonon strain coefficient b=−930cm −1 and the experimental total strain for all samples, regardless of the degree of the relaxation of the grade-up Si 1-x Ge x layer.

PMOS degradation with the blanket-stress-memory-technique (SMT) nitride layer on the (100) wafer with ?100? orientation has been observed, and the degradation mechanism is examined. The boron-doping loss from both the PMOS gate and the source/drain region during the SMT process is the root cause. In situ N2 plasma treatment before the SMT layer deposition has been implemented for the first time to recover PMOS performance on the ?100? wafer by reducing the boron-doping loss from the gate and the source/drain region. Reliability like PMOS NBTI has been examined, and no degradation is observed.

Hole mobility is significantly higher for silicon MOSFETs with channels along a <110> direction on the (110) plane than the usual (100) plane. Formation of (110) PMOS and (100) NMOS transistors is possible through use of Dual Substrate Orientation (DSO) integration. This paper describes a CMOS integration scheme to achieve bulk (110) PMOS and SOI (100) NMOS devices on the same substrate. Transistor results indicate a 130% improvement in PMOS Id,lin and 90% enhancement in Id,sat for long channel devices. Hole mobility and drive current anisotropy along the <110> and <100> channels on (110) plane was observed. There was no gate leakage or sub-threshold slope degradation indicating that the DSO integration results in high quality Si/SiON dielectric interfaces. PMOS enhancement from compressive channel stress is additive to that of orientation and compatible with the DSO integration.

Sputtered A1N films developed for piezoelectric resonators are extremely chemically reactive. As-sputtered films react with boiling water resulting in a complete loss of the AIN bond structure. Experiments to determine the effect on chemical stability of annealing the sputtered films at 1000 °C, indicate annealing in an oxidizing gas leads to partial oxidation of AlN. Annealing in an inert gas prevents oxidation but does not protect the films from attack by boiling water. Annealing in a reducing gas followed by annealing in an inert gas renders A1N films stable in boiling water. A1N film structure and composition have been studied via Refractive Index, XRD, SIMS, SEM, AES, XPS and FTIR evaluations.