Body-biasing is commonly used to regulate power/performance for modern integrated circuits. However, it has an additional soft error rate (SER) and single event latch-up (SEL) impact. The physics of bipolar action, charge collection mechanisms and drive current variation are explored to quantify the impact of body bias using a 90-nm technology. Results indicate that in certain cases body-biased operation can help achieve the elusive goal of lower power as well as lower SER and SEL. Practical design limits are proposed on the extent of well bias to achieve lower power and higher reliability, especially for high temperature automotive environments.

We present the first-ever commercially available microcontroller families built with innovative split-gate based NOR flash memory that uses silicon nanocrystals as the storage medium. The 32-bit mixed-signal low-power Kinetis microcontroller families have nanocrystal based flash memories (referred to as TFS for `Thin Film Storage') with a wide range of array sizes from 32KB to 1MB. In addition, the unique capability of TFS has enabled inclusion of fully configurable embedded EEPROM functionality called `FlexMemory', which also manages wear leveling for high endurance. The TFS memory has been optimized to deliver read access time of <;30ns, fast source-side injection programming (10-20μs), fast tunnel erase into the gate (1-20ms), robust high temperature data retention before and after cycling, endurance of at least 10K cycles for flash and effective endurance up to 10M cycles in the EEPROM mode. In addition, the microcontroller core, analog and flash modules have been developed to deliver performance, reliability, and low-power operations across a temperature range of -40C to 105C and full operation down to 1.7V from a single power supply.

In this paper, we present the first-ever commercially available embedded Microcontrollers built on 90nm-node with silicon nanocrystal memories that has intrinsic capability of exceeding 500K program/erase cycles. We also show that the cycling performance across temperature (-40C to 125C) is very well behaved even while maintaining high performance that meets or exceeds the requirements of consumer, industrial, and automotive markets. In specific EEPROM implementation, such high endurance is capable of delivering in excess of 200M data updates. In addition, we also demonstrate that the nanocrystal flash memory is highly scalable to the next generation nodes and the scaling can be accomplished without degradation of program/erase speed, endurance and reliability.

This paper reports on recent bitcell optimizations that improve drive current and program performance. The 16 Mb and 32 Mb array results are best to-date for nanocrystal memories and suggest a robust, reliable array operation.

Thin SiGe-channel confinement is found to provide significant control of the short channel effects typically associated with nonbandedge gate electrodes, in an analogous manner to ultrathin-body approaches. Gate workfunction requirements for thin-SiGe-channel p-type field effect transistors are therefore relaxed substantially more than what is expected from a simple observation of the difference between gate and channel work-functions. In particular, thin-SiGe channels are shown to enable cost-effective high-performance bulk CMOS technologies with a single gate workfunction near the conduction bandedge.

We report a CMOS-compatible embedded silicon-carbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (C-sub) epitaxial Si:C and laser spike annealing (LSA) for increased C-sub incorporation. 26% channel resistance (Rch) reduction and 11% Idlin-Ioff enhancement for 0.5% C-sub and 60% Rch reduction for 2.2% C-sub are demonstrated.

Using PMOSFETs with a range of built-in process induced stress and four-point bending characterization, we present evidence that the stress response of PMOSFETs increases with channel stress. A novel method incorporating the characterization data with channel stress simulation has been developed which shows excellent agreement between our prediction and measured transistor performance data for nitride etch stop layer splits. Our analysis indicates that PMOSFETs will continue to show increasingly effective performance enhancement at higher channel stress

We present a low cost, single metal gate/high-k gate stack integration, which provides a very high performing NMOS coupled with a counter-doped PMOS for a 45mn low power (LP) CMOS technology. Inversion To,. (T-inv)values of 16 angstrom/18 angstrom (NMOS/PMOS) result in gate leakage current densities of 0.1/0.01 A/cm(2) and enable self-heated drive currents of 850/325 mu A/mu m at InA/mu m off-state leakage and V-dd=1V (900/340 mu A/mu m non-self-heated). Additionally, the NMOS drive current of 1550uA/[mu m (1650 mu A/mu m non-self-heated) at an I-off= 100nA/mu m and V-dd=1.2V is the highest reported for a hafnium-based high-k gate stack. The approach is compatible with a dual-gate oxide (DGO) module for I/O devices and allows optimization for performance and power typically only possible in triple gate oxide architectures. (1).

We report on the optimized transverse and lateral boundaries of dual etch stop layer (dESL) stressors in both PMOS and NMOS achieved in 65nm SOI transistors. We demonstrate that this gives an additional ~20% performance gain in ring oscillators. The optimization takes into account the 1-D and 2-D geometry effects, including poly-pitch, and is in good agreement with stress simulations

We report, for the first time, on the 2D boundary effects in a high performance 65nm SOI technology with dual etch stop layer (dESL) stressors. 1D geometry effects, such as poly pitch dependence, and the implications on SPICE models and circuit design are also discussed. It will be shown that PMOS and ring oscillator performance can be significantly enhanced by optimizing the transverse and lateral placement of the dESL boundary