Co-Packaged Optics is a development of technology for high speed data switching, to be implemented widely in data center and high-performance computing architectures as a means to continue expansion of bandwidth and reduction of energy per bit. This development removes transceivers from the switch faceplate and replaces them with an optical link from the faceplate to transceiver PICs packaged on or near the ASIC switch substrate. Most approaches involve CW external lasers being carried over polarization-maintaining fiber to the PICs to be modulated for outgoing traffic. Lasers are active components with extremely high power densities and thus a relatively high failure rate, and they perform poorly at high temperatures such as prevail near the switch package. Therefore they will be remotely located or in removeable/front-panel pluggable packages that can be replaced with minimal disruption; this will require the use of optical fiber connectors. System reliability is significantly enhanced by using fewer, higher-power lasers, so very high powers are anticipated for these sources, up to and perhaps exceeding 250 mW, and any connector must be able to reliably tolerate these power levels over the lifetime of the laser or switch box. The use of expanded beam connectors reduces the optical intensity at exposed surfaces compared to PC connectors, and may mitigate some potential issues. We report on our initial studies to address this question of connector performance at these extreme conditions, with results on expanded beam single-mode connectors carrying high laser power in the O-band over many hundreds of hours.

A silicon photonic based transmitter and receiver chipset for 4x106Gb/s 400 GBASE-DR4 data rates is presented. Each channel of the transmitter chip reaches high extinction ratio and optical modulation amplitude (OMA) with a low TDECQ penalty in full compliance with the IEEE standard. The receiver chips possess high responsivity with low polarization dependent loss. The use of discrete III-V arrayed components hybridized onto the silicon platform and passive alignment of single-mode fibers provides a low-cost, compact and scalable solution extendable to even higher aggregate rates and channel count.

We have successfully demonstrated an ultra-compact WDM 400G-FR4 ROSA module integrated with silicon photonics circuits operating at 53.125Gbaud PAM4 signal with a sensitivity of -6.0dBm optical modulation amplitude at KP4 Pre-FEC-BER=2.4e-4.

We demonstrate passive 1×32 (de)multiplexers with 200GHz channel spacing that matches the ITU grid in the C and L bands. A flat-top 120GHz-wide 1dB passband, channel-to-channel crosstalk of <−30dB, and ~2.5dB insertion loss is measured.

An architecture is presented for realizing 1 Tbps datacenter interconnects using energy efficient silicon photonic ring modulators and QD-MLL. Both these components show excellent agreement with design parameters. High efficiency EO tuners are also reported.

We perform wafer-scale measurements of silicon photonics components using broadband (100nm+) edge couplers and reflecting optical fiber probes for the first time. We demonstrate <1dB/cm waveguide loss and 25GHz+ micro-ring modulators on 300mm wafers.

Recent integrated optical phased array architectures, results, and applications will be reviewed, including beam steering for LiDAR and communications, near-field optical manipulation, and holographic displays for augmented reality.

To meet the increasing demand for data communication bandwidth and overcome the limits of electrical interconnects, silicon photonic technology has been extensively studied, with various photonics devices and optical links being demonstrated. All of the optical data links previously demonstrated have used either heterogeneously integrated lasers or external laser sources. This work presents the first silicon photonic data link using a monolithic rare-earth-ion-doped laser, a silicon microdisk modulator, and a germanium photodetector integrated on a single chip. The fabrication is CMOS compatible, demonstrating data transmission as a proof-of-concept at kHz speed level, and potential data rate of more than 1 Gbps. This work provides a solution for the monolithic integration of laser sources on the silicon photonic platform, which is fully compatible with the CMOS fabrication line, and has potential applications such as free-space communication and integrated LIDAR.

Recent integrated optical phased array architectures, results, and applications will be reviewed. Beam-steering optical phased arrays monolithically integrated with on-chip rare-earth-doped lasers and heterogeneously integrated with CMOS driving electronics will be shown. Passive integrated optical phased arrays that focus radiated light to tightly-confined spots in the near field and that generate quasi-Bessel beams will be discussed. Finally, integrated-phased-array-based visible-light holographic displays will be proposed as a scalable solution towards the next generation of augmented-reality head-mounted displays; passive near-eye holographic displays, visible-light liquid-crystal modulators, and liquid-crystal-based visible-light phased arrays will be presented.

400G-FR4 silicon photonics transmit-receive chipsets, compatible with co-packaged-optics, on-board-optics, and pluggable form factors, were demonstrated with a combined bandwidth density of 94Gb/s/mm, energy efficiency of <10pJ/bit, and -5.4dBm OMA sensitivity at the KP4 pre-FEC-BER=2.4e-4.

We present an optical phased array with a record 8192 individually-addressed elements driven by flip-chip CMOS spanning a 100° × 17° field of view. The reticle-sized PIC+CMOS beam steering engine enables near cm-scale apertures for long-range applications.

The accuracy of conventional ADCs for high-frequency input signals is mainly limited by the sampling clock jitter. To address this issue, this paper demonstrates an ADC that uses low-jitter (<; 26 fs rms ) optical pulses to sample the input signal. A prototype two-channel ADC is realized in a 3D integrated platform with 65 nm CMOS and silicon-photonics connected using high-density TOVs. With optical pulses spaced at 250 ps (4 GS/s effective sampling rate), the ADC achieves SNDR of 40 dB near DC and 37 dB at 45 GHz input.

Thanks to the successful application of Si-based photonic integrated circuits (PICs) to data communications, demand for PICs has increased dramatically. As a result, integrated device manufacturers (IDMs), as well as foundries, have provided much improved capability and capacity since 2010. PIC foundries, in particular, offer capability that is accessible to users around the world and in a variety of technology platforms. This chapter is meant to teach the community what has advanced in the past decade to enable a suite of processes for different types of PICs, typically dedicated to a particular market demand. The chapter is not meant to describe the operation of a specific foundry, but rather, a vision of PIC foundries with examples from different institutions. After reading the chapter, the reader should have a better understanding of the advances that have enabled PIC foundry capabilities and the background to be able to interact with a PIC foundry.

With the growing demand for automotive LiDAR and the maturation of silicon photonics platforms, optical phased arrays (OPAs) have emerged as a key technology for solid-state optical beam-steering. In order to meet realistic automotive specifications with OPAs, > 500 antenna elements should work reliably under tight power and cost budgets. Existing multi-chip solutions necessitate expensive packaging and assembly to achieve high interconnect density. Even with 2-D monolithic integration, high-voltage drivers to deliver sufficient power to resistive phase shifters typically result in significant overhead in die area and limited power efficiency. In this article, we introduce a single-chip OPA realized through wafer-scale 3-D integration of silicon photonics and CMOS. Flexible and ultra-dense connections with through-oxide vias (TOVs) in our platform resolve the I/O density issue. Moreover, low-voltage L-shaped phase shifters and compact, efficient switch-mode drivers, connected vertically using TOVs, remove wiring/placement overhead and achieve a large active array aperture within a compact die. Our OPA prototype achieves wide-range 2-D steering over 18.5 degrees x 16 degrees by leveraging wavelength tuning and phase control, and array scaling up to 125 elements with a large aperture size of 0.5 mm x 0.5 mm and 0.15 degrees x 0.25 degrees beamwidth while consuming 20 mW/element average power. Since our system supports per-element independent phase control, increased sensitivity to process variations in L-shaped shifters is fully compensated by a simple calibration process.

Silicon photonics has been heralded for a number of high technology fields, but access to a high quality technology has been limited to vertically integrated design/fabrication companies, or fabless companies with significant resources to engage high volume fabs. More recently, research and development hubs have developed and released process design kits and multi-project wafer programs to lower the barrier. We present the first silicon photonics multi-project wafer (MPW) service produced in a state-of-the-art 300 mm fabrication facility. The MPW service is enabled by a best-in-class process design kit (PDK) which allows designers to layout and obtain photonic integrated circuits (PICs) that work properly on the first run. The fabrication of these circuits is carried out at the SUNY Polytechnic Institute which operates a world class 300 mm cleanroom that, besides silicon photonics, develops sub-7 nm CMOS architectures. The industrial-level management of this facility and its equipment provides high quality photonic devices which are repeatable from run-to-run along with rapid turnaround time. The devices that are available to designers via the process design kit are produced by Analog Photonics and have been verified on actual runs. The performance of these devices is comparable to the state-of-the-art and enables a wide variety of silicon photonic applications.

An advanced CMOS-compatible 300-mm-wafer silicon-photonics platform is introduced that consists of a silicon layer with eight doping masks, two silicon-nitride layers, three metal and via layers, a dicing trench for smooth edge-coupled facets, and a gain-film trench that enables interaction between the gain material and waveguide layers. The platform was used to demonstrate an electrically-steerable integrated optical phased array powered by an on-chip erbium-doped laser. Lasing with a single-mode output, 30 dB side-mode-suppression ratio, and 40 mW lasing threshold was shown, and one-dimensional beam steering with a 0.85 degrees x 0.20 degrees full-width at half-maximum and 30 degrees/W electrical steering efficiency was demonstrated. This system represents the first demonstration of a rare-earth-doped laser monolithically-integrated with an active CMOS-compatible silicon-on-insulator photonics system.

The realization of a low-cost and robust optical beam-steering platform is a key enabler for a number of applications, including light detection and ranging (LIDAR) and free-space optical communications (FSO). Optical phased arrays (OPAs) have emerged as a promising solution, due to advancements in photonic integrated circuits (PIC) foundry processes, which have enabled high-precision fabrication of PICs with a large number of components [1]–[3]. In order to meet steering range and directivity requirements in systems such as autonomous vehicles, a clear path to scaling OPAs to millimeter-scale apertures with thousands of tight-pitched antenna elements is critical. As the element count grows, independent phase control for each element becomes crucial since maintaining coherence between elements becomes more difficult due to process variations. Moreover, independent control allows for unique system capabilities, such as multi-beam formation and converging/adaptive beams, which makes OPAs a particularly attractive solid-state beamforming technology.

An updated process design kit (APSUNY PDKv3.0) is introduced with verified passive and active O+C+L band silicon photonics component libraries, which includes 50Gbaud (100Gbps) capable modulators, high yield splitters and detectors on 300mm SOI wafers.

Here we present extremely low connector-to-connector loss (≤3 dB) through silicon photonic chips using ultra-low loss (≤0.15 dB) splicing between SMF-28 and ultra-high numerical aperture (UHNA) fibers. The small MFD from the UHNA fibers enables strong coupling to hybrid TE/TM edge couplers achieving TM (TE) losses of 1.25 (2.35) dB per coupler and low polarization-dependent loss. Mode coupling simulations and tolerance are investigated to understand performance.