We demonstrate a UCIe Optical I/O Retimer for scale-up AI fabrics. It achieves 1.024Tbps of bidirectional bandwidth per optical port from one package to another, delivering an aggregate bandwidth of 8.192Tbps.

This paper presents connectorized in-package optical I/O chiplets with V-groove for passive fiber attach, enabling robust and scalable connectivity solutions for AI and high-performance compute. We demonstrate a process for ensuring known good chiplets using Ayar Labs’ TeraPHY™ optical I/O chiplet.

We present a 256Gbps WDM transceiver macro for use in co-packaged AI scale-out interconnects. The macro adopts a $8\lambda\times 32\text{Gbps}$ configuration to achieve 256Gbps per fiber. The transceiver macro operates error-free across a dynamic temperature ramp of 50-110°C, has >4dB optical link margin with $4\text{dBm}/\lambda$ input laser power, and consumes 3.45pJ/b ( $\text{TX}+\text{RX}$ ). All transmit, receive, thermal control, and optical components are monolithically integrated in a 45nm SOI process. An optical I/O chiplet with 8 WDM transceiver macros achieves <10 −15 BER without FEC across 90 hours of operation in a 4Tbps duplex link configuration.

8 and 16 wavelength optical sources for optical IO applications are reviewed. A new CW-WDM MSA compliant, 16 wavelength source operating from 20 to 100°C is presented.

Silicon photonics combined with complementary metal–oxide–semiconductor (CMOS) electronics leveraging wavelength-division multiplexing (WDM) are of interest for AI, optical computing, and high-speed Optical IO applications [1,2]. To power these applications, multi-wavelength light sources based on laser arrays [3] or mode locked lasers (MLL) have been proposed and demonstrated [4]. As optical sources mature, the CW-WDM multisource agreement (MSA) has emerged to define a set of wavelength grids and power levels so different applications can leverage a common set of laser technologies [5]. In this paper we demonstrate the first multi-wavelength optical source compliant with the CW-WDM MSA standard that operates from room temperatures through 100°C. The SuperNovaTM outputs 8 wavelengths across 8 fibers for a total of 64 optical carriers and complies with the 8+1 MSA wavelength plan (1 optional wavelength) with channels spaced at 400+/-100 GHz and output power within the Type 2 power class. The optical source is mode hop free with >40dB SMSR, <145 dB/Hz RIN, and <20 MHz linewidth across all channels and all operating conditions.

We demonstrate a CW-WDM MSA compliant multi-wavelength source driving an error-free WDM CMOS optical link. The SuperNova™ operates up to 100°C and outputs 64 optical carriers (8 wavelengths x 8 fibers), and together with the TeraPHY™ chiplet, drives up to 2 Tbps from a CMOS die.

Heterogenous co-packaging of optical I/O with compute, memory or switch nodes will deliver significant improvements in power, bandwidth and reach in data center and high-performance computing applications. A first-ever real-ized and validated 5.12 Tbps co-packaged FPGA with optical I/O is presented. The Multi-Chip Package integrates a 14nm FPGA die with five Ayar Labs TeraPHY™ optical I/O chiplets.

For the first time, we demonstrate an error-free, 128Gbps (8x16Gbps) optical transceiver using a microring-based wavelength-division multiplexed (WDM) architecture. The optical transceiver ran for 12 hours with zero errors, resulting in a measured bit-error rate of <1.45e-15 per optical lane. The total number of bits sent during this time was ~691 terabits per lane and ~5.5 petabits aggregate across all lanes.

The first 8 Tbps co-packaged FPGA with Silicon-Photonics IO is presented paving the way for co-packaged compute and optical-IO. The Multi-Chip Package integrates Stratix® 10 FPGA with up to five optical IO chiplets. © 2021 The Author(s).

We demonstrate an electro-optic platform enabling a direct optical I/O interface in an ASIC package. The $5.5\mathrm{x}8.9\mathrm{mm}^{2}$ chiplet uses the Advanced Interface Bus (AIB), a parallel digital interface, to communicate to a host ASIC and integrates high-speed digital/analog circuits, optical modulators, photodetectors, and waveguides. Transmitters and receivers demonstrate data-rates up to 25Gbps at 4.9pJ/bit (Tx+Rx) and <10−12 BER error-free operation. We show a 32-channel, 512Gbps aggregate (across 4 Tx ports) wavelength-division multiplexed (WDM) transmit demonstration from a TeraPHY chiplet, running at 16Gbps per wavelength and 8 simultaneous wavelengths per port.

In this article, we present TeraPHY, a monolithic electronic-photonic chiplet technology for low power and low latency, multi-Tb/s chip-to-chip communications. Integration of the TeraPHY optical technology with open source advanced interconnect bus interface enables communication between chips at board, rack, and row level at the energy and latency cost of in-package interconnect. This enables the design of logically connected but physically separated large-scale and high-performance digital systems. The copackaging integration approach is demonstrated by integrating the TeraPHY die into the Intel Stratix10 FPGA multichip package.

This paper presents a high-sensitivity, fully differential (FD) optical receiver (RX) for high-density system-on-chip applications. The high digital activity prominent in such applications creates common-mode and power-supply noise, which degrades the optical RX sensitivity. To suppress these noise sources and enhance the RX sensitivity, an optical RX is proposed that realizes FD operation by using a new resonant split-microring photodetector. The complete RX is implemented in a 45-nm SOI CMOS with no process changes. When aptly biased, the detector outputs FD photocurrent with <+/- 0.3% splitting error. It has 0.52-A/W responsivity and a bandwidth of 5.0 GHz. The RX circuit is optimized to achieve BER < 10(-12) at 12 Gb/s with an optical modulation amplitude (OMA) sensitivity of -18.2 dBm while consuming 7 mW. Compared with a conventional single-ended RX on the same test-chip, the proposed RX improves sensitivity from 13 to 7.9 mu App without reducing the bandwidth or significantly impacting the RX energy efficiency.

In this work, we provide an overview of System-in-Package (SiP) integration of an electronic-photonic chiplet fabricated in a commercial CMOS foundry. Assembly considerations, including co-packaging in a standard multi-chip module (MCM) package with a System-on-Chip (SoC), thermals, and fiber attach will be reviewed.

In this Letter, owing to an error during the production process, the author affiliations were listed incorrectly. Affiliation number 5 (Colleges of Nanoscale Science and Engineering, State University of New York (SUNY)) was repeated, and affiliation numbers 6–8 were incorrect. In addition, the phrase “two oxide thickness variants” should have been “two gate oxide thickness variants”. These errors have all been corrected online.

Integrating photonics with advanced electronics leverages transistor performance, process fidelity and package integration, to enable a new class of systems-on-a-chip for a variety of applications ranging from computing and communications to sensing and imaging. Monolithic silicon photonics is a promising solution to meet the energy efficiency, sensitivity, and cost requirements of these applications. In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our "zero-change" silicon photonics platforms in 45 nm and 32 nm SOI CMOS. The results indicate that the 45 nm and 32 nm processes provide a "sweet-spot" for adding photonic capability and enhancing integrated system applications beyond the Moore-scaling, while being able to offload major communication tasks from more deeply-scaled compute and memory chips without complicated 3D integration approaches.

We present a high bandwidth-density photonic interconnect platform that transmits 1.05 Tbps/mm(2) using 0.83 pJ/bit, integrated in a 45nm SOI process, and a high-density multi-wavelength laser source.

In this work, we provide an overview of the technology and architecture of a microprocessor chip with optical I/O. Zero-change photonics integration enabled the chip to be fabricated in a commercial electronics CMOS foundry.

A 64-bit dual-core RISC-V processor with vector accelerators has been fabr icated in a 45nm SOI process. This is the first dual-core processor to implement the open-source RISC-V ISA designed at the University of California, Berkeley. In a standard 40nm process, the RISC-V scalar core scores 10% higher in DMIPS/MHz than the Cortex-A5, ARM’s comparable single-issue in-order scalar core, and is 49% more area-efficient. To demonstrate the extensibility of the RISC-V ISA, we integrate a custom vector accelerator alongside each single-issue in-order scalar core. The vector accelerator is 1.8⇥ more energy-efficient than the IBM Blue Gene/Q processor, and 2.6⇥ more than the IBM Cell processor, both fabr icated in the same process. The dual-core RISC-V processor achieves maximum clock frequency of 1.3GHz at 1.2V and peak energy efficiency of 16.7 doubleprecision GFLOPS/W at 0.65V with an area of 3mm .

In this work, we present WaveLight, a monolithic silicon-photonics platform whereby a low latency reliable deterministic protocol with optical functions are designed directly into an existing high-volume CMOS process.