Described is a secure, multi-time programmable memory (MTPM) solution for the 14 nm FINFET node and beyond, which turns as-fabricated standard logic transistors into embedded non-volatile memory (eNVM) elements, without the need for any process adders or additional masks. These logic transistors, when employed as eNVM elements, are dubbed “Charge Trap Transistors” (CTTs). Outlined are the technological breakthroughs required for employing logic transistors as an MTPM. An erase technique, called “Self-heating Temperature Assisted eRase” (STAR), is introduced which enables 100% erase efficiency, as compared to <; 50% erase efficiency using conventional methods, in turn enabling MTPM functionality in CTTs. For the first time, hardware results demonstrate an endurance of > 10 4 program/erase cycles. Data retention lifetime of > 10 years at 125 °C and scalability to 7 nm have been confirmed.

Author(s): Khan, Faraz | Abstract: Described is a Multi-Time Programmable Memory (MTPM) solution, manufactured in a 14 nm bulk FINFET technology, which requires no process adders or additional masks, using Charge Trap Transistors (CTTs). Outlined are the technological breakthroughs required to support multi-time program and erase of CTTs for this secure embedded non-volatile memory (eNVM) technology. For the first time, hardware results demonstrate an endurance of g 103 Program/Erase cycles. Data retention lifetime of g 10 years at 125 °C and scalability to 7 nm has been confirmed.

The Charge Trap Transistor (CTT) technology is an emerging memory solution that turns as-fabricated high-k/metal gate (HKMG) logic transistors into secure, embedded non-volatile memory (eNVM) elements with excellent data retention and operation capability at military grade temperatures. In other words, the CTTs offer a completely process-free and mask-free eNVM solution for advanced HKMG CMOS technology nodes. In this letter, bitcell design to enhance programming efficiency and modeling of the charge trapping behavior of CTTs in 14 nm FinFET technology is discussed.

This paper describes the design and implementation of an 80-kb logic-embedded non-volatile multi-time programmable memory (MTPM) with no added process complexity. Charge trap transistors (CTTs) that exploit charge trapping and de-trapping behavior in high-K dielectric of 32-/22-nm Logic FETs are used as storage elements with logic-compatible programming voltages. A high-gain slew-sense amplifier (SA) is used to efficiently detect the threshold voltage difference ( $\Delta V_{\textrm {DIF}}$ ) between the true and complement FETs in the twin cell. Design-assist techniques including multi-step programming with over-write protection and block write algorithm are used to enhance the programming efficiency without causing a dielectric breakdown. High-temperature stress results show a projected data retention of 10 years at 125 °C with a signal loss of <30% that is margined in while programming, by employing a sense margining logic in the SA. Scalability of CTT has been established by the first demonstration of CTT-based MTPM in 14-nm bulk FinFET technology with read cycle time of 40 ns at 0.7-V VDD.

An 8Kx192b charge trap transistor one time programmable memory (OTPM) is designed and manufactured in GLOBALFOUNDRIES 14-nm bulk FinFET technology without process adders or additional masks. A write timer state machine issues multicycle 192b parallel programming with per bit overwrite protection to minimize stress conditions during a write. On-chip generated voltages are temperature dependent, enabling writes and reads at military grade temperatures. A differential current sense amplifier with self-biased margining circuitry enables programming the OTPM twin cell with known repeatable margin across process-voltage-temperature. Hardware qualification certifies the OTPM to a 10-year 105 degrees C data retention specification and <3 PPM end of life bit error rate pre-ECC.

The availability of on-chip non-volatile memory for advanced high-k-metal-gate CMOS technology nodes has been limited due to integration and scaling challenges as well as operational voltage incompatibilities, while its need continues to grow rapidly in modern high-performance systems. By exploiting intrinsic device self-heating enhanced charge trapping in as fabricated high-k-metal-gate logic devices, we introduce a unique multiple-time programmable embedded non-volatile memory element, called the `charge trap transistor' (CTT), for high-k-metal-gate CMOS technologies. Functionality and feasibility of using CTT memory devices have been demonstrated on 22 nm planar and 14 nm FinFET technology platforms, including fully functional product prototype memory arrays. These transistor memory devices offer high density (~0.144μm 2 /bit for 22 nm and ~0.082μm 2 /bit for 14 nm technology), logic voltage compatible and low peak power operation (~4mW), and excellent retention for a fully integrated and scalable embedded non-volatile memory without added process complexity or masks.

An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity. Multi-step verification with overwrite protection employs block-write and signal margin degradation (~30%) to satisfy 10 year retention at 105° C.

In this letter, charge trapping behavior in 22-nm technology high-k-metal-gate SOI CMOS logic devices is analyzed under various bias stress and self-heating conditions. It is observed that the charge trapping is not only dependent on the channel power density during stress, which is controlled by drain bias and device channel length, but is also strongly modulated by the device channel width. Thus, identical power densities in devices with different channel widths result in significantly different charge trapping behaviors. It is shown that device self-heating is strongly influenced by the device channel width and that the channel temperature during the charge injection process significantly impacts the magnitude and stability of the trapped charge. We discuss the implications of the findings for the application of high-k-metal-gate logic devices as embedded memory elements for non-volatile data storage in high-k-metal-gate CMOS technologies without added process complexity.

We explore the use of oxygen vacancies for nonvolatile data storage by trapping electrons in the high-k, gate dielectric layer of NFETs. Programming is performed via channel carrier injection and is erased by tunneling. 64Kb arrays were constructed and reliability is demonstrated.