An 8K×192b One Time Programmable Memory (OTPM) is designed and manufactured in a 14nm FinFET technology without process adders or additional masks. A Differential Current Sense Amplifier (DCSA) and dynamic adaptive 192b parallel programming results in a <; 3 PPM bit error rate, and supports a 10 year 105°C retention specification.

An 8Kx192b charge trap transistor one time programmable memory (OTPM) is designed and manufactured in GLOBALFOUNDRIES 14-nm bulk FinFET technology without process adders or additional masks. A write timer state machine issues multicycle 192b parallel programming with per bit overwrite protection to minimize stress conditions during a write. On-chip generated voltages are temperature dependent, enabling writes and reads at military grade temperatures. A differential current sense amplifier with self-biased margining circuitry enables programming the OTPM twin cell with known repeatable margin across process-voltage-temperature. Hardware qualification certifies the OTPM to a 10-year 105 degrees C data retention specification and <3 PPM end of life bit error rate pre-ECC.

A family of embedded DRAMs which are fabricated in 45nm SOI technology is presented. The fast eDRAM has 64 b/BL and achieves a random cycle time of 1.3ns for V DD = 1.00V and typical process. The dense eDRAM has 128 b/BL and operates in multi-bank modes up to 1.67GHz for V DD = 1.0V and nominal process. The staggered - folded BL architecture with BL twisting over both the array and SAs is described as well as a novel wordline timer which generates a 75% duty cycle signal from a 50% duty cycle clock.

An embedded DRAM macro fabricated in 65 nm CMOS achieves 1.0 GHz multi-banked operation at 1.0 V yielding 584 Gbits/sec. The array utilizes a 0.1 1 mum2 cell with 20 fF deep trench capacitor and 2.2 nm gate oxide transfer gate. Concurrent refresh allows for high availability via a second bank address. At-speed test and repair is accomplished with a new hierarchical BIST architecture. Measured random cycle time exceeds 333 MHz at 1.0 V with functional operation from 750 mV to 1.5 V and densities up to 36.5 Mbits.

This work describes a 500-MHz compiled eDRAM macro offered in a 90-nm logic-based process. The macro architecture is optimized for high bandwidth while enabling compilation in bank and data-word dimensions. A direct write scheme simultaneously improves random bank cycle time and row access time without signal loss. The benefits of ground sensing, reference cells, and bitline twisting was reviewed. A variable stage pipeline extends the macro bandwidth while offering flexibility in clock frequencies. The redundancy system is modified to support direct write and piping. Finally, BIST was enhanced to utilize electrically blown fuses, enabling one-touch test and repair. Hardware results was presented.

High performance devices available in a logic-based embedded DRAM process can be used to significantly improve eDRAM performance. However, random access cycle time of conventional eDRAMs remains around 6 ns. In this work, a novel destructive-read architecture that reduces the random access cycle time of an eDRAM by delaying the data write back operation to a later cycle is demonstrated. A single-ended direct sensing is employed to further speed up the random access cycle time of the eDRAM to 2.9ns.