Vicilogic links online learning, assessment, and prototyping with remote Field Programmable Gate Array (FPGA) hardware. Vicilogic provides online training and practice in digital systems design, RISC-V computer architecture and applications, and FPGA-based data and pixel processing applications. The Vicilogic course browser interacts with transparently with an array of remote FPGA, controlling and probing real remote hardware signals. This enables presentation of a visually rich, interactive learn-by-doing pedagogy, supporting guided learning, self-paced training, component sandboxes, knowledge checks, automated hardware application execution demos and remote FPGA prototyping. The Vicilogic course builder provides course tutors with the facility to create new course modules and to select individual lessons to create a tailored, indexed course to align with their curriculum. This paper presents the current Vicilogic course portfolio, available to Electronic and Computer Engineering and Computer Science audiences. The recently developed FPGA-based data and pixel processing applications course is described, which uses a structured, top-down, and finite state machine-based design and documentation methodology. Application examples include image thresholding, Sobel edge detection and a breakout game. The course provides a lesson for each application component, with downloadable AMD Xilinx Vivado project and VHDL model templates. Vicilogic lessons reference HDLGen, an open-source client application, developed by the Vicilogic team. HDLGen provides a wizard for fast, automated creation of System on Chip HDL models, testbench, Electronic Design Automation project and Tool Command Language scripts. The paper also presents the extended integrated development and debug environment (IDE), used in the reported Vicilogic RV32I RISC-V Online Tutor course. This IDE provides remote RISC-V assembly program application development and debugging. A remote RISC-V breakout game application is illustrated.

This paper presents the open source HDLGen-ChatGPT application, working in tandem with ChatGPT-3.5, the free online large language model (LLM) chat interface. The tools enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) projects. EDA tools check the generated HDL syntax, simulate and synthesise HDL models, and follow the steps to FPGA hardware prototyping. The tools exploit a formal, top-down design and test specification documentation process, domain knowledge, and the flexibility of LLMs, for HDL code generation. Results are included for a hierarchical RV32I RISC-V processor design. Process steps are illustrated for the RISC-V 32 x 32-bit register bank component. The process typically requires only minimal manual HDL capture or editing, and often none at all. URLs to tutorial videos for the complete RISC-V design are provided on the GitHub project repository. The paper evaluates the results and provides HDLGen-ChatGPT and ChatGPT usage recommendations. The tools can be applied in digital systems training programmes, with reduced emphasis on the assessment of HDL model and testbench capture and generation, while maintaining strong emphasis on the assessment of system design, test planning and documentation, HDL simulation verification/debug, and analysis of synthesised netlists.

This paper presents the RISC-V Online Tutor course which provides structured, self-paced RISC-V architecture and applications training. The course browser transparently interacts with remote RISC-V hardware, implemented on an FPGA array. The course is implemented and supported by the reported vicilogic platform which provides online learning, remote FPGA prototyping and course builder. Lessons control remote hardware input signals, probe all RISC-V processor signals and overlay signal widgets on interactive course diagrams. The strategy provides a visually-rich, interactive learn-by-doing experience. The paper presents the course structure, and examples of the interactive lesson pedagogy. User experience, opinion and analytics are presented for a group of 45 users. Results indicate a high level of user satisfaction, and effective independent learning and achievement. Course availability is timely, with the growing interest in the RISC-V open-source Instruction Set Architecture, the call for training materials by RISC-V International, and the increasing demand for practical online learning systems, particularly during the Covid-19 pandemic.

This paper presents the use of the viciLogic viciLab tool suite for prototyping of audio digital signal processing (DSP) hardware on remote or locally connected PYNQ Systems on Chip (SoCs), along with flexible computer control software interfaces. The tool suite enables rapid prototyping of DSP hardware components, including demonstration, control and visualisation of components on local or remote hardware. Hardware components can be developed directly in existing hardware description languages (HDLs) or using higher-level design interfaces such as MathWorks HDL coder. Two configurable software control interfaces are presented: a low-level console builder facilitating fast graphical user interface (GUI) creation for hardware interaction, along with script-based automation; and a high-level Python-based GUI console creator integrates audio sampling, automated DSP hardware effect selection and SoC control, audio streaming and playback, and real-time waveform graphing. The two interfaces presented in this paper are illustrated through a series of DSP examples of increasing complexity: 8- and 16-tap FIR filters (with user-created VHDL model source); distortion and tremolo DSP functions (developed MathWorks HDL coder VHDL model source); and combinations of these components.

The Si elegans platform targets the complete virtualization of the nematode Caenorhabditis elegans, and its environment. This paper presents a suite of unified web-based Graphical User Interfaces (GUIs) as the main user interaction point, and discusses their underlying technologies and methods. The user-friendly features of this tool suite enable users to graphically create neuron and network models, and behavioral experiments, without requiring knowledge of domain-specific computer-science tools. The framework furthermore allows the graphical visualization of all simulation results using a worm locomotion and neural activity viewer. Models, experiment definitions and results can be exported in a machine-readable format, thereby facilitating reproducible and cross-platform execution of in silico C. elegans experiments in other simulation environments. This is made possible by a novel XML-based behavioral experiment definition encoding format, a NeuroML XML-based model generation and network configuration description language, and their associated GUIs. User survey data confirms the platform usability and functionality, and provides insights into future directions for web-based simulation GUIs of C. elegans and other living organisms. The tool suite is available online to the scientific community and its source code has been made available.

This paper presents viciLogic 2.0, a scalable, distributed online learning, hardware prototyping, client application and course creator platform for System on Chip (SoC)-based digital systems. User applications transparently link to a device in an array of Xilinx PYNQ-Zl or-Z2 SoC hardware in the cloud. The viciLogic prototype builder toolsuite (which integrates with the Xilinx Vivado industry-standard EDA tools) automates online (and local) SoC digital logic hardware prototyping, with integrated viciLogic user interface. The platform supports real-time user hardware input signal control and automated signal control, and probes the state of all user design internal and output signals. This enables the creation of responsive client applications and smart browser-based courses. Online course functions include guided lessons, SoC signal state monitoring for automatic course progression, knowledge checks, and user sandbox. The prototype builder uses source VHDL or Verilog projects created, simulated and synthesised in Vivado. The builder parses and modifies the HDL model to provide signal observability, integrates SoC resources (ARM, AXI interconnect, peripherals and viciLogic IP), and (using Vivado) generates the SoC hardware configuration bitstream and design metadata. The paper describes the viciLogic 2.0 server architecture, SoC prototype builder tool flow, client application creator, and online course creator. Two demonstration applications are presented, a counter course lesson step and a client application (16-bit single cycle computer, with IDE).

This paper presents the development of a method to implement real-time displacement detection and measurement in video feeds. The main results of this research lie in the applicability of the method on low-power and low-resource platforms. The secondary objective of the research described here, is the preparation of a framework to use the motion detection method with the on-board execution unit of mobile robots or UAVs. This will yield increased accuracy in adaptive localization and obstacle avoidance capabilities in these systems.

For students of digital logic design and applications, prototyping of FPGA/SoC digital logic hardware requires knowledge of design principles, hardware description language (HDL) modelling and testbenching, and Electronic Design Automation tools. There is limited availability of locally-installed (or in-house) tools which offer high level wizard-based parameterisable graphical digital logic design capture, with auto-generation of HDL. This paper presents ICCapt, a browser-based parameterisable graphical digital logic design capture wizard. ICCapt enables fast design capture, with auto-generation of synthesisable HDL models. ICCapt integrates with the viciLab cloud FPGA/SoC hardware prototyping and client application console creation toolsuite. Students can build hardware prototypes in the cloud, and visually interact with remote hardware in real time, using their ICCapt-generated block diagrams in the client console. ICCapt helps students to better understand the hierarchical structure of digital logic design and HDLs. The paper presents a series of design-to-prototype examples, and describes the ICCapt web tool architecture and its functions.

This demo presents viciLogic2.0, a scalable, distributed, online learning and prototyping platform for gold-standard, basic-to-advanced digital logic design and prototyping education. viciLogic2.0 uses a Xilinx PYNQ [1] reconfigurable System on Chip (SoC) cloud array, and locally-connected SoCs. Client and browser applications provide control and visualisation of the state of all user design signals in real time, within the automatically-allocated and configured remote programmable logic hardware. Each SoC includes an Ethernet-connected ARM-based server which facilitates FPGA resource selection, configuration and control, and remote user interaction. This enables the creation of responsive, interactive client local and browser applications, connected directly to hardware, and online technology enhanced learning applications.

Abstract The paper presents three embedded soft-core processor architectures, developed by the authors to be easily implementable while yielding low digital resource usage. These architectures will be compared and contrasted between each-other by introducing a special testing method, based on control algorithm implementations. For reference, the same testing and comparison has been implemented on a well established architecture, too, on the Xilinx PicoBlaze processor. Measurement results and application suggestion are given in the concluding section.

Research Department, Petru Maior University of Tîrgu Mureş, Romania, e-mail: lbako@ms.sapientia.ro Bio-Inspired Electronics and Reconfigurable Computing (BIRC) Research Group, National University Ireland Galway, Ireland, e-mail: fearghal.morgan@nuigalway.ie Electrical Engineering Department, Faculty of Technical and Human Sciences, Sapientia Hungarian University of Transylvania, Romania, e-mail: tiha@ms.sapientia.ro 4 Department of Informatics, Faculty of Sciences and Letters, Petru Maior University of Tîrgu Mureş, Romania, e-mail: ecalin@upm.ro

Hardware faults are becoming more frequent due to geometric scaling, reducing the reliability and lifespan of devices. Current fault-tolerant approaches use redundancy or a central controller to detect and/or repair faults. However, these methods are also susceptible to faults. Astrocytes have been shown to facilitate biological self-repair in silent or near silent neurons in the brain by increasing the Probability of Release (PR) in healthy synapses. Astrocytes modulate synaptic activity, which leads to increased or decreased PR. To date, this has been proven with computational modelling and therefore the next step is to replicate this self-repair process in hardware to provide self-repairing systems. One of the key challenges for hardware neuro-glia networks is the facilitation of scalable communication between interacting neurons and astrocyte cells. This paper contributes a low-level Networks-on-Chip (NoC) ring topology for astrocyte to neuron/synapse communication which provides a scalable solution to this interconnect challenge. It builds upon our previous FPGA-based Hierarchical Networks-on-Chip (HNoC) and establishes preliminary communication building blocks to facilitate the development of distributed self-repair hardware systems. FPGA results demonstrate that the new ring topology provides a good trade-off between low area/interconnect wiring overhead and communication speed for the relatively slow-changing data between astrocyte and neurons.

Spiking neural networks (SNNs) are well suited for functions such as data/pattern classification, estimation, prediction, signal processing and robotic control applications. Whereas the real-world embedded applications are often multi-functional with orthogonal or contradicting functional requirements. The EMBRACE hardware modular SNN architecture has been previously reported as an embedded computing platform for complex real-world applications. The EMBRACE architecture employs genetic algorithm (GA) for training the SNN which offers faster prototyping of SNN applications, but exhibits a number of limitations including poor scalability and search space explosions for the evolution of large-scale, complex, real-world applications. This paper investigates the limitations of evolving real-world embedded applications with orthogonal functional goals on hardware SNN using GA-based training. This paper presents a novel, fast and efficient application prototyping technique using the EMBRACE hardware modular SNN architecture and the GA-based evolution platform. Modular design and evolution of a robotic navigational controller application decomposed into obstacle avoidance controller and speed and direction manager application subtasks is presented. The proposed modular evolution technique successfully integrates the orthogonal functionalities of the application and helps to overcome contradicting application scenarios gracefully. Results illustrate that the modular evolution of the application reduces the SNN configuration search space and complexity for the GA-based SNN evolution, offering rapid and successful prototyping of complex applications on the hardware SNN platform. The paper presents validation results of the evolved robotic application implemented on the EMBRACE architecture prototyped on Xilinx Virtex-6 FPGA interacting with the player-stage robotics simulator.

This paper presents an embedded implementation of a hardware-efficient method for motion information extraction from a video signal. The high computing cost of gradient-based methods makes their implementation in compact devices for real-time applications challenging. We present our achievements in implementing a novel, simplified version of a gradient-based method, using an FPGA circuit-based system for on-line Sobel edge detection and edge displacement-based optical flow computation. The image data is acquired from a dedicated embedded camera transmitted to the reconfigurable platform. The design and implementation steps of the devised method are presented, followed by the description of the system's setup and measurement results. The yielded results are compared to similar implementations. These results lead to possibilities in using the developed system for the enhancement of indoor mobile robot localization.

This paper presents a prototype web-based Graphical User Interface (GUI) platform for integrating and testing a system that can perform Low-Entropy Model Specification (LEMS) neural network description to Hardware Description Language (VHDL) conversion, and automatic synthesis and neuron implementation and testing on Field Programmable Gate Array (FPGA) testbed hardware. This system enables hardware implementation of neuron components and their connection in a small neural network testbed. This system incorporates functionality for automatic LEMS to synthesisable VHDL translation, automatic VHDL integration with FPGA logic to enable data I/O, automatic FPGA bitfile generation using Xilinx PlanAhead, automated multiFPGA testbed configuration, neural network parameter configuration and flexible testing of FPGA based neuron models. The prototype UI supports clock step control and real-time monitoring of internal signals. References are provided to video demonstrations.

The use of advanced driver assistance systems is becoming increasingly common in road-going vehicles. One application of these driver assistance systems is in the automated detection of vulnerable road users, such as pedestrians, using automotive far-infrared imagery. Detection of pedestrians in infrared imagery can be quite difficult because of a number of factors such as the environment, pedestrian behaviour and also the physical limitations of currently available infrared sensors. This study presents a comprehensive review of the literature currently available in the area of pedestrian detection techniques in automotive infrared imagery. The challenges associated with automated detection of pedestrians in the automotive domain are first discussed. An overview of the general structure of pedestrian detection algorithms is then presented, followed by an in-depth analysis of existing literature in the area. Some proposals for future research in the area based on the methods described in this study are then offered.

The use of night vision systems in vehicles is becoming increasingly common, not just in luxury cars but also in the more cost sensitive sectors. Numerous approaches using infrared sensors have been proposed in the literature to detect and classify pedestrians in low visibility situations. However, the performance of these systems is limited by the capability of the classifier. This paper presents a novel method of classifying pedestrians in far-infrared automotive imagery. Regions of interest are segmented from the infrared frame using seeded region growing. A novel method of filtering the region growing results based on the location and size of the bounding box within the frame is described. This results in a smaller number of regions of interest for classification, leading to a reduced false positive rate. Histograms of oriented gradient features and local binary pattern features are extracted from the regions of interest and concatenated to form a feature for classification. Pedestrians are tracked with a Kalman filter to increase detection rates and system robustness. Detection rates of 98%, and false positive rates of 1% have been achieved on a database of 2000 images and streams of video; this is a 3% improvement on previously reported detection rates.

Biological neural systems are powerful, robust and highly adaptive computational entities that outperformconventional computers in almost all aspects of sensory-motor integration. Despite dramatic progress ininformation technology, there is a big performance discrepancy between artificial computational systemsand brains in seemingly simple orientation and navigation tasks. In fact, no system exists that can faithfullyreproduce the rich behavioural repertoire of the tiny worm Caenorhabditis elegans which features one of thesimplest nervous systems in nature made of 302 neurons and about 8000 connections. The Si elegans projectaims at providing this missing link. This article is sketching out the main platform components.

Urinary incontinence is defined as the inability to stop the flow of urine from the bladder. In the US alone, the annual societal cost of incontinence-related care is estimated at 12.6 billion dollars. Clinicians agree that those suffering from urinary incontinence would greatly benefit from a wearable system that could continually monitor the bladder, providing continuous feedback to the patient. While existing ultrasound-based solutions are highly accurate, they are severely limited by form-factor, battery size, cost and ease of use. In this study the authors propose an alternative bladder-state sensing system, based on Ultra Wideband (UWB) Radar. As part of an initial proof-of-concept, the authors developed one of the first dielectrically and anatomically-representative Finite Difference Time Domain models of the pelvis. These models (one male and one female) are derived from Magnetic Resonance images provided by the IT'IS Foundation. These IT'IS models provide the foundation upon which an anatomically-plausible bladder growth model was constructed. The authors employed accurate multi-pole Debye models to simulate the dielectric properties of each of the pelvic tissues. Two-dimensional Finite Difference Time Domain (FDTD) simulations were completed for a range of bladder volumes. Relevant features were extracted from the FDTD-derived signals using Principle Component Analysis (PCA) and then classified using a k-Nearest-Neighbour and Support Vector Machine algorithms (incorporating the Leave-one-out cross-validation approach). Additionally the authors investigated the effects of signal fidelity, noise and antenna movement relative to the target as potential sources of error. The results of this initial study provide strong motivation for further research into this timely application, particularly in the context of an ageing population.

Caenorhabditis elegans features one of the simplest nervous systems in nature, yet its biological information processing still evades our complete understanding. The position of its 302 neurons and almost its entire connectome has been mapped. However, there is only sparse knowledge on how its nervous system codes for its rich behavioral repertoire. The EU-funded Si elegans project aims at reverse-engineering C. elegans‘ nervous system function by its emulation. 302 in parallel interconnected field-programmable gate array (FPGA) neurons will interact through their sensory and motor neurons with a biophysically accurate soft-body representation of the nematode in a virtual behavioral arena. Each FPGA will feature its own reprogrammable neural response model that researchers world-wide will be able to modify to test their neuroscientific hypotheses. In a closed-feedback loop, any sensory experience of the virtual nematode in its virtual environment will be processed by sensory and subsequently interconnected neurons to result in motor commands at neuromuscular junctions at the hardware-software interface to actuate virtual muscles of the virtual nematode. Postural changes in the virtual world will lead to a new sensory experience and thus close the loop. In this contribution we present the overall concepts with special focus on the virtual embodiment of the nematode. For further information and recent news please visit http://www.si-elegans.eu.