Assessment of design implications due to degradation of CMOS devices is increasingly required in the latest technologies. This paper presents selected topics relevant to realize an efficient design-in reliability methodology in the latest generation CMOS technologies. NBTI is discussed in terms of characterization using On-The-Fly (OTF) methodology. Extension of OTF method is discussed using bias patterns to gain insights into NBTI under analog operation. A reliability simulation methodology is discussed against requirements for optimization and integration within an existing design flow. The features of this methodology are illustrated using some simple design examples.

We have proposed a new methodology to study both DC and AC NBTI effects taking into account both the recoverable property of the degradation and the electrical parameter legitimacy in each electrical configuration. In this new framework, characterization phases induce no effect (neither recovery nor extra-damage) on the degradation. For DC NBTI with a partial/uniform recovery, a generalized universal recovery modelling has been proposed for the first time to estimate the recovery amount. This modelling is particularly useful to calculate the recovery time needed after a stress period to reach a (decrease) degradation amount. For AC NBTI case, NBTI has been directly studied on circuits parameters opening new promising perspectives in term of reliability criteria

This work shows that the Channel Hot Carrier (CHC) degradation for a p-MOSFET consists of two different regimes. At low V-g, the degradation is dominated by hot electrons produced by impact ionization. The hot electrons are responsible for the creation of both interface traps and electron traps within the oxide. At high V-g a NBT-induced Hot Carrier effect is evidenced as well as an anomalous CHC effect. This work should help understanding the CHC degradation of pMOSFET as well as determining the worst case degradation.

This work presents new perspectives of the NBTI in advanced technology. Both modelling and characterization of NBTI are investigated for the maturation of the reliability management in advanced node technologies. A physical-based VT instability model is presented considering interface trapped charges, fixed charges and oxide trapped holes effects. Finally, we discuss on the lifetime concept in the case of recoverable NBTI-induced degradation.

Permanent damage induced by Channel Hot-Carrier (CHC) injections have been distinguished from the charge–discharge of near-interface traps in ultra-thin gate-oxide (1.6 nm) MOSFETs. It is shown that usual DC accelerating techniques mostly devoted to CHC damage at large voltage conditions cannot be used alone for low supply voltage (VDD=1V) MOSFETs. This arises from the charging of slow traps which induces a worst-case of damage which is relaxing in different ways depending on the discharging bias and cold phases. This is particularly more severe under hole injections in P-channel than under electron injections in N-channel MOSFETs in relation to the smaller mobility of holes and to the gate-oxide nitridation which induces deep traps from the oxide valence band. The true effects of the distinct damage and relaxations are further analysed using AC stresses which are required for the worst-case determination in advanced logic circuits. This is further evidenced by the determination of the effective quasi-static time factors dependent on the alternated damaging, discharging, and relaxing periods involved in ultra-thin gate-oxide MOSFETs operating at low voltage.

We focus in this study on the negative bias temperature instability (NBTI)-induced /spl Delta/N/sub IT/ phenomenon and we point out its relative gate-oxide thickness (T/sub OX/) dependences. Studies are carried out in a large T/sub OX/ range, comparing the gate-oxide quality which was grown with or without nitrogen incorporation. We have developed an oxide field (F/sub OX/) dependence for /spl Delta/N/sub IT/ and we show the two opposite effects of T/sub OX/ on the threshold voltage shift (/spl Delta/V/sub T/). Simulation of both effects shows a good correlation with experimental results in pure oxide and confirms the reduced interface trapped charge effect in /spl Delta/V/sub T/ in nitrided devices. Results enable us to extrapolate the NBTI impact when T/sub OX/ is varied which allows us to determine in a useful way the security margin during the gate-oxide process optimization.

An overview of evolution of transistor parameters under negative bias temperature instability stress conditions commonly observed in p-MOSFETs in recent technologies is presented. The physical mechanisms of the degradation as well as the different defects involved have been discussed according to a systematic set of experiments with different stress conditions. According to our findings, a physical model is proposed which could be used to more accurately predict the transistor degradation. Finally, the influence of different process splits as the gate oxide nitridation, the nitrogen content, the source/drain implant and poly doping level on the NBTI degradation is investigated and discussed with our present understanding.

This work gives new insights of negative bias temperature instability (NBTI) characterization methodologies in advanced CMOS technology. NBTI is well-known to seriously limit the circuit performances in p-channel MOSFETs, in relation to both interface trap generation and hole trapping in the gate oxide. Hole detrapping from oxide traps during electrical parameter extractions, also called a recovery phenomenon, is unanimously acknowledged to be the most critical phenomenon avoiding a proper characterization of the effective damage. We point out here new NBTI evaluation techniques using pulsed voltages on the gate and on the drain to characterize NBT degradation and quantify recovery effects in the usual methodology.

We propose a new methodology to characterize the negative bias temperature instability (NBTI) degradation without inherent recovery. The extracted parameters are the linear drain current, the threshold voltage and the transconductance. We compare the new and the usual methodologies and show a logarithmic time dependence of both the degradation and the recovery. The hole trapping (detrapping) is directly correlated to the VT degradation (recovery), and plays the main role in the NBTI in ultra-thin gate-oxide PMOSFET's.

We have developed in this work a new characterization methodology which includes stressing and measurement in a single experimental step. This overcomes the influence of the hole detrapping effect in ultra-thin gate-oxides (T/sub OX/=1.4-1.6 nm) and enables comparison of gate-oxide nitridation impacts on negative bias temperature instability (NBTI). This new approach offers possibilities to measure the whole degradation and to improve DC NBTI characterization in operating logic circuits.

This work gives an insight of the degradation mechanisms during negative and positive bias temperature instability in advanced CMOS technology with a 2nm gate-oxide. We focus on generated interface traps and oxide traps to distinguish their dependencies and effects on usual transistor parameters. NBTI and PBTI in NMOS and PMOS have been compared a possible explanation for all configurations has been suggested. Relaxation and temperature effects under NBTI were also investigated showing different behaviors of the two components of threshold voltage shift, i.e. the interface traps and the oxide traps.

We propose a new methodology to characterize the negative bias temperature instability (NBTI) degradation without inherent recovery. The extracted parameters are the linear drain current, the threshold voltage and the transconductance. We compare the new and the usual methodologies and show a logarithmic time dependence of both the degradation and the recovery. The hole trapping (detrapping) is directly correlated to the V/sub T/ degradation (recovery), and plays the main role in the NBTI in ultra-thin gate-oxide PMOSFET's.