Silicon carbide (SiC) has emerged as a leading material for high-power applications. However, the high density of interface states (D it ) at the SiO 2 /SiC interface still constrains the performance and reliability of MOSFET devices. In this work, lateral 4H-SiC MOSFETs subjected to post-deposition annealing (PDA) in nitric oxide (NO) of different durations were investigated through capacitance-voltage measurements, supported by an analytical model and an iterative MATLAB-based D it extraction algorithm. The results demonstrate that NO PDA effectively reduces D it not only near the conduction band edge but also towards the valence band, yielding improved channel mobility (µ FE ) and enhanced threshold voltage stability.

ABSTRACT The integration of 2D molybdenum disulfide (MoS2) with gallium nitride (GaN) enables many interesting (opto)electronic applications, such as heterojunction diodes and UV/visible photodetectors, whose performances crucially depend on the thickness uniformity, strain and doping of MoS2 films and on the energy band alignment at the interface. This work reports a multiscale electro‐optical characterization of large size (∼100 µm) monolayer (1L) MoS2 flakes directly grown on n‐GaN and, for comparison, on a SiO2/Si substrate by liquid‐precursors‐intermediated chemical vapor deposition. XPS and micro‐Raman mapping revealed a superior crystalline quality, lower average strain ε ≈ −0.06% and higher n‐type doping n ≈ 0.7 × 1013 cm−2 for 1L‐MoS2 grown on GaN, as compared to MoS2 grown under identical conditions on the amorphous SiO2 surface. Nanoscale current‐voltage mapping by C‐AFM showed a significantly reduced Schottky barrier (ΦB = 0.57 ± 0.06 eV) at 1L‐MoS2/GaN interface as compared to the bare GaN surface. This result, combined with a MoS2/n‐GaN work function difference WMoS2‐WGaN ≈ 360 meV evaluated by KPFM mapping, revealed a type‐I band alignment at the heterojunction. Finally, photocurrent measurements on macroscopic Ni/n‐GaN, Ni/MoS2/n‐GaN and Ni/MoS2/SiO2 lateral devices under illumination with photon energies from ∼2 to ∼5 eV showed superior electro‐optical performances of Ni/MoS2/n‐GaN heterojunctions both in the visible and UV range.

An Al2O3/AlN stack deposited via Atomic Layer Deposition (ALD) methods as a gate insulator for silicon carbide (4H-SiC) has been investigated, focusing on the effects of different Al2O3 deposition processes on the nitride layer. In particular, dielectric stacks, consisting of a 10 nm AlN interface (001)-oriented layer directly grown on a 4H-SiC substrate and in 20 nm of additional amorphous Al2O3 layers were synthesized in sequential deposition runs by thermal ALD (T-ALD) or plasma-enhanced ALD (PEALD) methods. The evolution of the phenomena occurring at the Al2O3/AlN interfaces has been established by in situ ellipsometry measurements. Strong effects of the oxygen plasma because of the O-Al-N bond formation have been clearly observed and corroborated by ex situ structural and electrical characterizations, especially in the case of the plasma-enhanced Al2O3 process. In particular, the Al2O3/AlN bilayer grown by the Al2O3 T-ALD method exhibited good insulating behavior and an 8.7-high dielectric constant was measured. By contrast, the Al2O3/AlN bilayer grown by the Al2O3 PEALD method demonstrated poor insulating properties.

In this work, the atomic layer deposition (ALD) of an ultra-thin AlN film on the surface of monolayer EG grown on-axis 4H-SiC(0001) substrates has been investigated as a function of the number of ALD cycles. The formation of a homogeneous film with a 10 nm thickness and crystalline wurtzite structure was obtained after 320 cycles, as demonstrated by atomic force microscopy (AFM) mapping, X-ray photoelectron spectroscopy (XPS) and X-ray diffraction. Raman mapping revealed a significant reduction in the native compressive strain of as-grown EG (ε ≈ −0.36%) with increasing ALD cycles, down to a value of −0.16% after full coverage. Finally, Kelvin Probe Force Microscopy (KPFM) surface potential mapping allowed the evaluation of energy band alignment of the AlN/EG heterojunction, with a conduction band offset of ~2.6 eV between the crystalline AlN film and the underlying EG. Such a large offset confirms AlN as a promising gate dielectric for EG-based devices.

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Basal plane dislocations (BPDs) represent one of the most detrimental defects in 4H-SiC epitaxial wafers, causing forward voltage degradation in bipolar and power FET devices through the formation and expansion of Shockley-type stacking faults (SSFs). This expansion is driven by the recombination-enhanced dislocation glide (REDG) mechanism during forward bias operation. Despite efforts to mitigate BPD effects by converting them into threading edge dislocations (TEDs) via buffer layer engineering, throughout the epitaxial growth SSFs can still nucleate and propagate, particularly under high current injection. This work presents a comprehensive analysis combining electrical characterization, fault localization technique, Scanning Electron Microscopy (SEM) and micro-photoluminescence (μ-PL) to investigate SSF formation, crystallographic features, and their impact on device performance. The results underscore the critical role of advanced diagnostics and epitaxial process optimization in controlling SSF-related degradation and improving the reliability of SiC power devices.

The high bandgap of AlScN makes it difficult to achieve ohmic contacts with a low specific contact resistance (rho(c)) to AlScN/GaN heterostructures. High rho(c) increases the on-resistance of the high-electron-mobility transistor fabricated from these heterostructures and reduces the achievable current densities. This work presents an ohmic recess process and Ti/Al/Ni/Au metallizations with a rho(c) of 8.83 & times; 10(-5) Omega cm(2) after annealing at 900 degrees C. Interestingly, time-of-flight secondary ion mass spectrometry reveals that out-diffusion of Sc from the barrier to the metal surface occurs at anneal temperatures above 700 degrees C. While this structural metamorphosis does not show a strong impact on rho(c), it leads to an increase in the on-resistance and gate leakage currents, as well as to a decrease in the maximum drain current of HEMTs. At an anneal temperature of 600 degrees C, no thermal degradation was observed and rho(c) as low as 13.4 & times; 10(-5) Omega cm(2) are achieved.

This paper investigates the forward conduction mechanism of W-based Schottky diodes on AlGaN/GaN heterostructures across a temperature range of 25-150 degrees C. Current-Voltage measurements carried out at different temperatures (I-V-T), allow to identify two coexisting mechanisms for charge transport. At lower bias the conduction mechanism is ruled by tunneling (TU), with a characteristic energy of E-00 = 75 meV extracted from the temperature dependence of the ideality factor. At higher bias the Thermionic Emission (TE) mechanism dominates, thus revealing the presence of an inhomogeneous barrier that increases from 0.77 to 0.94 eV with increasing the measurement temperature. An ideal barrier of 1.22 eV was extrapolated for a unitary ideality factor. Structural and electrical analyses performed at nanoscale level revealed the presence of a density of defects (dislocations) in the order of 4 x 10(9) cm(-2). Conductive Atomic Force Microscopy (C-AFM) provided local electrical information, uncovering a significant correlation between the observed electrical characteristics and the nanoscale defect distribution. This detailed insight highlights the crucial role of the electrical characteristics of defects in influencing the tunneling current component at low bias, thereby providing valuable context for understanding the electrical behavior and performance of microscopic devices.

In this work, we investigated the electrical properties evolution of Mo/4H-SiC Schottky contacts following thermal annealing treatments at temperature up to 950 °C. The electrical characterization under forward and reverse bias revealed a reduction of the barrier height from 1.45 eV (as-deposited contact) to 1.30 eV (950°C-annealed contact), with the presence of inhomogeneity in the contact, while the leakage current followed a thermionic-field emission (TFE) model after annealing at 750 °C and presented a significant increase for the 950°C-annealed contact. The electrical characterization was associated with microstructural analyses, which highlighted an enlargement of the grains forming the structure of the Mo-film and the presence of voids near the Mo/4H-SiC interface. These observations can be at the base of the variation in the electrical behavior of the contact.

Semiconductor transition metal dichalcogenides (TMDs), such as MoS 2 , are currently regarded as key-enabling materials for sub-1 nm channel transistors, beyond-complementary metal–oxide–semiconductor electronic and optoelectronic devices and sensors. Owing to this wide application potential, several bottom-up and top-down synthesis approaches for these materials have been explored so far. Despite the huge progresses in scalable deposition methods (such as chemical vapor deposition, metal–organic chemical vapor deposition), exfoliated layers from bulk crystals still represent the benchmark for record electronic properties of TMDs. Among exfoliation approaches, metal-assisted mechanical exfoliation emerges as the most effective method to separate large-area (mm 2 to cm 2 ) single-crystalline monolayer membranes of TMDs (and many other 2D materials) from the parent bulk crystals. This paper reviews the state-of-the-art in this field, from current understanding of MoS 2 exfoliation mechanisms on Au (considered as a model system), to the main device applications of as-exfoliated and transferred large-area MoS 2 membranes (including Au/MoS 2 /Au memristors, MoS 2 photodetectors, and field-effect transistors). Perspectives of this method in the realization of arrays of 2D heterojunction devices, including Moirè superlattice devices, and open challenges for its widespread application are finally discussed.

In this paper we demonstrate a fully optimized process flow for silicon carbide semi-Superjunction (semi-SJ) Schottky barrier diodes, achieving high performance with readily available foundry technology. Using SF6-based etching, we fabricated 7 gm deep trenches with smooth, well-angled sidewalls (80-85) and optimized implantation of the trench bottom and sidewalls. Scanning capacitance and atomic force microscopy, combined with TCAD simulations, confirmed the successful sidew all doping implantation. The resulting structures are expected to exhibit an RDSON of 6.2 m Omega.cm(2) and a 4 kV breakdown voltage, outperforming planar diodes. These advancements enable seamless integration of semi-SJ technology into SiC power devices, paving the way for next-generation high-voltage applications.

This paper reports on the structural and electrical properties of AlGaN/GaN heterostructures grown onto 2°-off-axis silicon carbide (4H–SiC) epitaxial layers. The quality of the grown heterostructures was assessed by a combination of different analytical techniques, revealing a density of conductive dislocations in the order of 1 × 109 cm−2. Electrical characterizations of test patterns and transistors provided insights into the transport properties in the two-dimensional electron gas channel, demonstrating a high current density and a field effect mobility (μFE) of about 1800 cm2/Vs. The temperature dependence of μFE allowed us to identify optical phonon scattering as the dominant transport mechanism in the system at high temperature. In addition to demonstrating the suitability of 2°-off-axis 4H–SiC epilayers for the growth of functional AlGaN/GaN high electron mobility transistors, these results provide useful insights for device manufacturers aiming at the monolithic integration of novel GaN devices onto SiC epitaxial layers.

In this paper, we investigated the effects of the processing parameters, such as deposition methods, annealing temperature, and metal thickness, on the electrical characteristics of Ti/4H-SiC contacts. A reduction of the Schottky barrier height from 1.19 to 1.00 eV following an increase of the annealing temperature (475–700 °C) was observed for a reference contact with an 80 nm-thick Ti layer. The current transport mechanisms can be described according to the thermionic emission (TE) and thermionic field emission (TFE) models under forward and reverse biases, respectively. The comparison with an e-beam evaporated Ti(80 nm)/4H-SiC contact did not show significant differences for the forward characteristics, while an increase of the leakage current was observed under high reverse voltage (>500 V). Finally, a thickness variation from 10 to 80 nm induced a reduction of the Schottky barrier height, due to the reaction occurring at the interface with a Ti-Al region extended up to the 4H-SiC surface. In addition to a deeper understanding of the Schottky barrier properties, this work is useful for the development of Schottky barrier diodes with tailored characteristics.

The integration of dielectrics with two-dimensional (2D) materials by scalable approaches represents a key requirement and one of the open challenges for the future industrialization of 2D-based electronics. This paper provides an overview of the role played by dielectrics in different graphene- and 2D semiconductors-based architectures, including 2D materials encapsulation, recently demonstrated ultra-scaled and three-dimensional (3D) stacked 2D-Field Effect Transistors (FETs) for post-silicon logic application, and tunnel transistors targeting ultra-high frequency (THz) operation. Furthermore, different classes of dielectrics suitable for the integration with 2D materials have been reviewed, including layered dielectrics (such as h-BN) and non-layered ionic crystals (such as CaF 2 ) with van der Waals interface on 2D materials, and high-k insulators deposited by atomic layer deposition (ALD). The advantages and disadvantages of each kind of dielectric in terms of permittivity, breakdown field, interface quality with 2D materials, as well as scalability of the integration approaches have been benchmarked. A special focus will be given on ALD, which still represents the only industrially compatible approach enabling scalable integration of high-k insulators. Currently available approaches to promote uniform ALD growth on the inherently inert surface of 2D materials have been extensively discussed, highlighting new trends and perspectives in this field.

Two-dimensional (2D) transition metal dichalcogenides (TMDs) ternary alloys, such as MoxW1-xS2, are very appealing for the possibility of continuously tuning their excitonic bandgap by the composition. However, the deposition of ultra-thin (monolayers or few-layers) alloys with laterally uniform composition on large area represents a main challenge of currently adopted synthesis methods. In this work, we demonstrated the growth of highly uniform Mo0.5W0.5S2 bi-layers on cm2 size SiO2/Si substrates by employing a simple and scalable approach, i.e. the sulfurization of a pre-deposited ultra-thin Mo/W stack at a temperature of 700 degrees C. Comparison of Mo(1.2 nm)/SiO2, W(1.2 nm)/SiO2, and Mo(1.2 nm)/W(1.2 nm)/SiO2 samples after identical sulfurization conditions revealed very different results, i.e. (i) a uniform monolayer (1L) MoS2 film, (ii) separated multilayer WS2 islands, and (iii) a uniform bilayer (2L) Mo0.5W0.5S2 film. This indicates how W surface diffusion and coalescence on SiO2 surface plays a main role in WS2 islands formation, whereas the reaction between S vapour with Mo films or Mo/W stacks represents the dominant mechanism for the formation of MoS2 and the MoWS2 alloy. Micro-photoluminescence (PL) mapping of the obtained 2L-Mo0.5W0.5S2 film showed an excellent uniformity of light emission on large area with an exciton peak at 1.97 eV, significantly blue-shifted with respect to PL emission of 1L-MoS2 at 1.86 eV. Such highly uniform optical properties make the grown MoWS2 alloy very promising for optoelectronic applications.

Strain-dependent electronic and optical properties are one of the most appealing features of 2D semiconductors, like monolayer (1L) MoS2. However, measuring and controlling the homogeneity of strain within the channel is crucial for next-generation MoS2 field-effect transistors (FETs). This article reports a multiscale investigation of backgated FETs fabricated using large-area 1L MoS2 flakes grown by liquid-precursor-intermediated chemical vapor deposition on SiO2/Si substrates. The devices exhibit very attractive properties for ultra-low power applications, such as an I on/I off > 106 and a normally off electrical behavior. The combination of temperature-dependent analyses of the FET transfer characteristics and nanoscale resolution potential mapping by Kelvin probe force microscopy shows a fully depleted MoS2 channel at V G = 0 and an effective Schottky barrier ΦB,FB = 0.21 eV at flatband voltage V FB = 17.9 V. An inhomogeneous tensile strain (ε) distribution along the channel length is revealed by micro-Raman and photoluminescence (PL) mapping, with a reduced ε and blue-shifted PL energy close to the Ni/Au source/drain contacts, suggesting a biaxial compression of 1L MoS2 induced by metal deposition. The implications of these observations on the effective mass meff variation along the channel and the current injection from source/drain contacts have been discussed in the perspective of future ultra-scaled-devices applications.

This paper reports on the effect of a sulfurization thermal process of the silicon carbide surface on the properties of Ni/4H-SiC Schottky barrier. In particular, the incorporation of sulfur (S) in the 4H-SiC near-surface region was observed at the process performed at 800 °C, without any significant effect on the surface morphology. On the other hand, Ni/4H-SiC Schottky contacts fabricated on the sulfurized 4H-SiC surface showed a 0.3 eV reduction of the average barrier height with a narrower distribution, with respect to the untreated sample. These results were explained by an increase of the 4H-SiC electron affinity after sulfurization, and a Fermi level pinning effect.

This work explores a key challenge in power device fabrication: the formation of ohmic contacts on p-type 4H-silicon carbide (SiC). We demonstrate a selective, low thermal budget approach using single titanium (Ti) metallization combined with pulsed laser annealing (PLA), as an alternative to both metallic multilayer stacks and conventional high-temperature annealing. By applying PLA with fluences above 3.6 J/cm2, Ti contacts exhibit linear current-voltage (I-V) behavior, indicating effective ohmic contact formation, with over 50% improvement in conduction observed at 3.8 J/cm2. Cross-sectional transmission electron microscopy (TEM) and elemental mapping reveal that higher fluences promote deeper SiC consumption, and the formation of a continuous, epitaxially regrown SiC layer, bonded to a uniform titanium carbide (TiC) layer extended deeper into the p-doped region. This structure supports efficient charge transfer and strong interfacial bonding. Furthermore, increasing fluence drives the transient liquid phase composition from Ti-rich toward a more balanced Ti-Si-C composition, promoting the formation of ternary phases enriched in Si and C that enhance interfacial stability and electrical performance. This work demonstrates that PLA offers precise control over interfacial reactions and contact microstructures, offering a scalable, selective, and thermally efficient approach for ohmic contacts on p-type 4H-SiC, advancing the development of high-performance, next-generation SiC-based power electronics.

Stacked aluminum oxide/aluminum nitride (Al2O3/AlN) layers were deposited on n-type (0001) 4H-SiC by atomic layer deposition (ALD) processes. The structural and chemical properties have been investigated and are consistent with the growth of similar to 9 nm oriented (0001) AlN layer, and an upper 20 nm amorphous Al2O3 layer. The entire Al2O3/AlN stack was electrically characterized and compared with respect to a single Al2O3 layer having the same total thickness. The Al2O3/AlN bilayer exhibited a higher dielectric constant (kappa = 8.7), a significant reduction of the oxide trapped charges (N-OT) from 7.8 x 10(12) to 1.8 x 10(12) cm(-2), as well as a decrease of a factor 2 of the interface traps density (D-it) compared with the Al2O3 single layer values. A large positive flat band voltage shift was observed in the C-V curves acquired on MIS capacitors. The comparison of the behaviour of MIS capacitors fabricated on both n-type and p-type 4H-SiC demonstrated that deep interface states (near the 4H-SiC mid gap) acting as acceptors or donors for the n-type and p-type MIS contribute to the observed behavior. This hypothesis has been also corroborated by TCAD simulations.