In this paper, we apply parallelism by 4x of analog signal processors to the design of a bandpass sigma-delta modulator. We show that the overall speed of the modulator is increased without increasing the speed requirement of the individual building blocks. Several architectures are considered in terms of their resilence to implementation details such as mismatch and gain errors. A switched capacitor circuit is also presented for the proposed modulator.

This paper reports on high-level low-power design techniques for a sinc decimation filter. At the heart of these techniques is the minimization of the computational complexity, by the elimination of redundant and irrelevant computations. Proper ordering of the filtering and down-sampling operators can achieve a five times reduction in the computational complexity. The effect of the datapath width optimization on the numerical accuracy and the computational complexity of the sinc decimator is also considered.

Several high-level low-power design techniques have been incorporated in the design of a decimation filter for software radio. These include; operation minimization, multiplier elimination and block deactivation. Analysis and simulation results indicate that these techniques can achieve a 4 times reduction in power dissipation. An interleaved multiplier-accumulator array is used in the lowpass filter. The decimation filter designed has a programmable resolution, that varies from 12 to 20 bits. The entire decimation filter has been designed in a 3.3 Volt 0.5 /spl mu/m CMOS technology.

Several low-power design techniques have been applied to the design of a power efficient multiplier-accumulator (MAC) array. The addition operation has been interleaved into the multiplier array. The MAC array is designed to have a programmable resolution so that the blocks corresponding to the least significant bits can be deactivated when a lower resolution is sufficient. The multiplier-accumulator has been designed in a 3.3 Volt 0.5 /spl mu/m CMOS technology.

Reducing power consumption has become an important issue in many design problems. However, in some cases this should be done without affecting the speed of operation. In this paper we present a division algorithm which minimizes the number of add/sub operations. By splitting a single iteration of the algorithm into two steps we are able to reduce the clock period and make the execution time independent of quotient digits. The redundancy of the signed-digit quotient representation is exploited to reduce the comparison precision and use a CSA. This reduces the hardware complexity (hence lower power consumption) and reduces the propagation delay (hence faster operation). Finally, a comparison is given between the proposed and existing algorithms. The proposed algorithm reduces the power consumption by 15% over radix 4 division algorithm and by 45% over the radix 2 division algorithm.

This paper describes a video compression algorithm that has a reduced computational complexity. The subband video compression algorithm uses a simplified analysis/synthesis filter bank and a vector quantization coding algorithm. The use of the simplified analysis/synthesis filter banks reduces the power dissipation by 23 times over other algorithms at the expense of a 4 dB reduction in the signal to noise ratio. The vector quantization algorithm is a computational algorithm instead of the power consuming memory lookup algorithms.

The demand for multimedia mobile terminals has created a need for low power implementation of video compression algorithms. In this paper we consider different implementations for the discrete cosine transform. The effect of pipelining and parallelism on reducing the power dissipation is considered for fast discrete cosine transform algorithms, as well as ROM-based algorithms.