Soft error resilience has become an essential design metric in electronic computing systems as advanced technology nodes have become less robust to high-charged particle effects. Designers, therefore, should be able to assess this metric considering several software stack components running on top of commercial processors, early in the design phase. With this in mind, researchers are using virtual platform (VP) frameworks to assess this metric due to their flexibility and high simulation performance. In this regard, herein, this goal is achieved by analysing the soft error consistency of a just-in-time fault injection simulator (OVPsim-FIM) against fault injection campaigns conducted with event-driven simulators (i.e. more realistic and accurate platforms) considering single and multicore processor architectures. Reference single-core fault injection campaigns are performed on RTL descriptions of Arm Cortex-M0 and M3 processors, while gem5 simulator is used to multicore Arm Cortex-A9 scenarios. Campaigns consider different open-source and commercial compilers as well as real software stacks including FreeRTOS/Linux kernels and 52 applications. Results show that OVPsim-FIM is more than 1000× faster than cycle-accurate simulators and up to 312× faster than event-driven simulators, while preserving the soft error analysis accuracy (i.e. mismatch below to 10%) for single and multicore processors.

Software reliability is an essential design metric in emerging large-scale multiprocessor embedded systems. Designers should identify soft error susceptibility of multiple applications executing in parallel early in the design time to ensure reliable system operation. This work proposes a non-intrusive fault injection engine that enables to conduct bespoke soft error analysis, allowing to identify and understand the soft error propagation through the processing elements (PEs). The proposed fault injection campaign evaluates the impact of soft errors considering real benchmarks in an RTL model of a distributed-memory NoC-based multiprocessor. Experiments demonstrate that 19% of soft errors are propagated to other PEs, where 31.6% of them led to erroneous computation and 58.4% to a system crash. Thus, the fault analysis must consider not only its local effect on the processor and memory but also how the fault propagates to other system components.

Compiler technology plays an important role in embedded applications, performance and power efficiency. Compilers provide software engineers with a wide variety of optimization settings (i.e., flags), which can be used to either configure debugging and warning messages or to achieve code optimization. While the use of optimization flags can substantially improve the performance of embedded application, their impact on soft error resiliency remains unclear. This paper investigates the impact of compiler optimization flags (i.e., -O1, -O2, -O3, and -Os) on soft error reliability of a MIPS processor running 24 benchmarks with up to 2.2 million instructions. The results show that the -Os level increased the soft error resilience to 75% of the application set when compared to the -O0 level. Moreover, -Os level provided enhancements up to 3.1x.

Many-core systems are increasingly popular in embedded systems due to their high-performance and flexibility to execute different workloads. These many-core systems provide a rich processing fabric but lack the flexibility to accelerate critical operations with dedicated hardware cores. Modern Field Programmable Gate-Arrays (FPGAs) evolved to more than reconfigurable devices, providing embedded hard-core processors with several IP cores. While FPGAs provide a rich reconfigurable hardware fabric, only one or two embedded hard-core processors are available to execute complex software applications. Therefore, modern FPGAs offer the possibility to merge the benefits of many-core systems with the reconfigurability of FPGAs. The goal of this paper is to present an infrastructure to implement many-core systems in modern FPGAs. An embedded hard-core processor is used to manage the many-core area, and to communicate with a host computer. A functional proof-of-concept system is presented, paving the way to connect dedicated hardware IPs into the NoC.

Operating CMOS circuits at subthreshold supply voltages is an attractive solution for substantial energy reduction, at the expense of strong timing performance degradation, for a broad range of battery operated appliances. One of the challenges of this approach in current technology nodes is the reduced available noise margin when operating at low supplies. This paper evaluates the Static Noise Margin (SNM) to ensure reliable estimations in subthreshold CMOS circuits. The evaluation starts with a DC simulation of cells, providing a guideline on how its inputs should be stressed. The analysis shows that improperly employing the DC simulation may lead up to 70% worst results, thereby underestimating the SNM. The DC simulation methodology was applied herein to three different techniques, to identify which can reduce the SNM pessimism without overestimating. To extended the range of assessment, and to allow more accurate results, Monte Carlo simulations are used to evaluate the impact of both process and temperature variations on SNM for 15 different pairs (combinations) of CMOS logic cells. Results suggest that the maximum-square technique to define SNM is the most suitable for CMOS logic circuit operating in subthreshold. Those methods are validated through extensive simulation experiments with cells in a 65-nm CMOS bulk technology.

This paper presents the design and analysis of HF-RISC, a 32-bit RISC processor, targeting voltage scaling applications. We start proposing a design flow that enables the processor to operate at multiple voltage levels and explore how this flow enables designers to leverage the advantages of low voltage designs. Next, we present a set of case study designs of HF-RISC in a 28nm FD-SOI technology assessing their area, performance and power figures. Using the collected data we discuss how our flow can enable better design space exploration for voltage scaling applications and define guidelines for achieving lower power and better power efficiency. Accordingly, the obtained results indicate that the proposed flow allows 9.5% lower power overall and 25.5% better energy efficiency in HF-RISC design.

Advances in design integration have enabled the integration of large Multiprocessor Systems-on-Chip (MPSoC). Such systems are prone to the execution of complex applications if high degree of parallelism is employed on the communication infrastructure. Network-on-Chip (NoC) has emerged as a new communication paradigm for large MPSoCs with advantages such as the increase of reliability on components interactions. However, device's integration may convey few shortcomings during MPSoC manufacturing and operation, for instance, the vulnerability to faults. This paper describes Phoenix, which is a direct mesh NoC with fault detection scheme. The proposed architecture explores a fault-tolerant mechanism, which is implemented in a distributed manner as a fault monitor on processors and routers. Results demonstrate that Phoenix can be scalable in view of the stabilization time regarding to faults incidence, allowing MPSoC operation even with the occurrence of a large number of faults.